SystemVerilog for Verification

Sledgehammer to crack a nut? – Use right tools for right class of design errors/bugs

2011-12-10T10:58:00.001-08:00

I am sure you have heard this phrase before – “A sledgehammer to crack a nut”; the below picture describes it all!

Would you use a HUGE hammer to crack a small, tiny nut?

(If you are further interested in this phrase read: http://www.phrases.org.uk/meanings/sledgehammer-to-crack-a-nut.html).

I recently had a small design error introduced in a piece of RTL as below: It is an interrupt masking logic, code snippet as below:

Note the use of “ANDing” logic – simply, AND- mask with data to produce result.The subtlety in Verilog/System Verilog is that you have 2 seemingly similar operators for doing AND operation;

The logical AND: &&
The bitwise AND: &

Given the “loose” data type checking, assignment rules etc. one can get away by using either one of the above many-a-times. In the above case the user used:

result = data && mask;

With result being a vector the above is a “logical/design error” but usually a Verilog compiler would let this go through (as it is not an error as per LRM).

Now one can “verify” this by writing a testbench, simulate, look at waveform and debug. Depending on luck and the expertise of the engineer, it could take some 30-minutes to few hours. But as a Verification power-house CVC suggests to rethink – use the right tool/technology for the right class of design errors. These are things that are very easy for a static verification technology such as HDL-Linting to flag in less than a minute.

For instance, let’s try the above code with a popular Linter – ALINT from Aldec (http://www.aldec.com/products/alint/).

ALINT has nice rule sets pre-packaged for various policies such as STARC (http://www.starc.jp/index-e.html). It produces the following:

This will trigger 2 rules:
- rule about logic operation having a vector operand
- rule about bit width mismatch in the assignment - LHS vs RHS.

ALINT: Warning: test.v : (4, 1): Module "top". "STARC_VLOG.2.1.4.5" Logical operator has vector argument(s). Use bit-wise operators for multi-bit arguments and logical operators only for 1-bit arguments. Level: Recommendation 1.
ALINT: Warning: test.v : (4, 1): Module "top". "STARC_VLOG.2.10.3.4" Assignment source bit width "1" is less than destination bit width "8". Upper bits of the right-hand side will be filled with zeroes. Match bit widths exactly to improve the readability of the description. Level: Recommendation 2.

Now from a business perspective too – this is a far better option for your management – usually LINT tools are far cost efficient than full blown SystemVerilog simulator(s) such as Aldec’s Riviera-Pro http://www.aldec.com/Riviera

So next time when you receive a RTL code to verify, do yourself a favor by running a quick Lint run before looking for “hard bugs” that demand popular, powerful techniques such as Constrained-random, coverage-driven, UVM based etc.

BTW – CVC offers training sessions (http://www.cvcblr.com/trainings) on Aldec’s ALINT and HDL-Lint in general. Contact us (http://www.cvcblr.com/about_us) to see how we can help your teams!

Happy Verification ahead!

UVM with VMM – first trial of true inter-operability

2011-12-09T11:30:00.001-08:00

As noted in our recent blog article http://www.cvcblr.com/blog/?p=362 UVM is the first genuine step in the industry towards verification inter-operability. But it has a long way to go before all the VIPs get migrated to UVM – if they do. So there is a strong need to leverage on existing code base such as VMM, OVM & UVM.

Below is a code snippet that shows how we can use both VMM & UVM messaging schemes in same env/code base. As such the code is not magic, is it? But do watch below for the real MAGIC..

If not for the inter-op kit, the above code would spit the messages from 2 different schemes and make it very hard for end user to keep track, customize etc.

With UVM & VMM loggers being separate and not “inter-operating” the following user issues may arise:

1. Different formatted messages coming at different lines, making it hard, ugly to read, analyze

2. Complicating data-mining of log files as there are 2 different formats now in same log file

3. Error, Warning counts distributed leading to unreliable FAIL/PASS detection

4. Any customization done by user on formatting needs to be done multiple times

5. Sending to different log files not as easy as it involves 2 different base classes now!

Again there are more, let’s get solutions on the table. Here comes the MAGIC: With VCS, try:

The log file now combines the `vmm_note into `uvm_info “magically” and unifies it for the users!

There is much more to this inter-op kit, see: http://www.vmmcentral.com/uvm_vmm_ik/

Enjoy UVM and more..

Verification inter-operability beyond UVM

2011-12-09T11:05:00.001-08:00

As industry gets ready for adopting UVM with SystemVerilog, there are several practical combinations that come to the fore. One of the important concerns is about the existing code base/VIPs that can be “reused as-is”, yet benefit from various UVM features. For instance consider a VMM based VIP being plugged into a new UVM based env. Several user requirements/expectations arise:

1. Can the UVM & VMM co-exist in same simulation?

2. Can we leverage on single messaging scheme – instead of both `uvm_error & `vmm_error counting on their own, how do we unify them?

3. Can UVM phasing control/synchronize the vmm_xacotr::start/stop_xactor?

4. How does the UVM-Objection work with VMM-Consensus?

5. How do we talk from VMM-channel to UVM components and vice-versa?

6.How does the UVM ACTIVE/PASSIVE mechanism control VMM xactors underneath?

7. Does UVM config mechanism affect the VMM, if yes, how, if not then what do we do?

I am sure there are more. But just enough to get you worried! Thankfully the problem seems to have been acknowledged by the EDA vendors and potential solutions have started emerging. For instance the recently released VMM/UVM inter-op kit from Synopsys is at: http://www.vmmcentral.com/uvm_vmm_ik/

Another common requirement from many customers is the ability to mix multiple modeling & verification languages with UVM. Cadence recently donated its version of UVM ML (Multi-Language) to Accellera for potential extension. This contains UVM-SystemC via TLM 2,0 and UVM-e for integrating IEEE 1647-E based eVCs to UVM. Though the industry has publically seen only Cadence’s Specman supporting IEEE 1647-E language, if John’s ESNUG were to be trusted (why not BTW?, see: http://www.deepchip.com/items/0495-02.html), it may be soon that all major vendors release E-support.

As noted in our recent blog, http://www.cvcblr.com/blog/?p=361 the upcoming 2012 year seems to be quite interesting for Verification technologies.

Reusing functional coverage from block to system level – LSI @ SNUG India

2011-06-24T11:38:00.001-07:00

Last week at SNUG India, LSI presented a good paper on the topic of Functional Coverage reuse (See: http://www.synopsys.com/Community/SNUG/India/Pages/Abstracts.aspx?loc=India&locy=2011#TA1)

Challenges and Approaches for Functional Coverage in SOC Verification Environments
Manikandan Subramanian, Ron Jacob, Sasidhar Dudyala, Srishan Thirumalai [LSI]

This paper describes the complexity in using block level functional coverage at top level and pitfalls and approaches to aid reuse. This also describes controllability on coverage infrastructure from block level to SOC level and how UVM-EA helped in building the layered testbench infrastructure that can be reused.

What I really liked about this is the level of maturity that the SystemVerilog adoption that this paper indicates in India – while functional coverage is one of the top few powerful features in System Verilog, its adoption has been traditionally slower than what we wished. Especially with the boatload of features, knobs/options to control/fine tune, it is clearly one of those features that is waiting to be explored in greater detail. In this paper Ron laid out a nice architecture for “coverage reuse” across levels of verification. The architecture he & his team proposed can be captured into 3 classes:

Config class – to configure “How much do you want”
Coverage class – to capture “what and all you want”
Coverage collector class – to sample the coverage points

In a way the last 2 points have been stressed by VMM for years, and we at TeamCVC have been recommending it to our customers for years.

Specifically during our popular System Verilog training sessions such as VSV (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) we compare this to an athletic race and describe how the “field meters” placed/planted in the filed actually measures the speed while the runners/athletes simply RUN RUn & RUN!

Now compare this to a classical VMM environment:

The environment with all the components form the “field” while the “transactions” that flow through match the real “athletes”. It makes a lot of sense to plant the “measuring meters” (in this case the “coverage collectors and the coverage models” away from the actual transactions.

This is what Ron’s team experienced too. Though there are some ACC technologies such as ECHO in VCS that traditionally worked better (see: http://www.cvcblr.com/blog/?p=9) with transactions “embedded with covergroups”, VCS’s ECHO has come a long way and has supported VMM style covergroups as well.

The next big challenge that Ron addressed was the “reusability” and need to “control” the amount of coverage at System Level from block level. He had several good guidelines for the users, recommend highly to take down his paper and keep it handy at work! While some of the “sample_cov” overriding can be better done using SystemVerilog 2009 updates to built-in sample() function, a lot needs to be still done. For instance how do we override a full coverage model/covergroup/coverpoint/bins/cross etc. at System Level?

Ron’s approach was to add disable bits – yes, better than not having it, but it doesn’t scale up. Several years back Vera added such AOP/OOP style extensions to covergroups, but due to slow user adoption, this was never ported to SystemVerilog. Talk to Arturo Salz – friendly known as the “Father of Vera HVL” by many if you are interested.Basically the extensions are to allow things like:

Add extra coverpoint/bin/cross
Delete/drop a block level coverpoint/bin/cross
Re-define the entire covergroup etc.

Now – where do we go from here – IEEE-SA invites sincere participation from end-users to set directions, drive language features/enhancements via active participation. See: https://mentor.ieee.org/stds-india/bp/StartPage to know more.

Meet TeamCVC at next week SNUG India DCE booth

2011-06-16T13:17:00.001-07:00

If you live in India, specifically Bangalore and work in the field of VLSI, it is hard to miss the well attended SNUG event every year. Just like last year, this year’s SNUG hosts the popular DCE - Designer Community Expo

http://www.synopsys.com/Community/SNUG/India/Pages/DCE.aspx

TeamCVC (www.cvcblr.com) will be at Verification track booth and you are welcome to stop by for a range of surprises, quiz & gifts including our various books (www.systemverilog.us). TeamCVC also has a paper co-authored by our CTO Srini (www.linkedin.com/in/svenka3) along with Kishor @Intel and Amit @SNPS, see abstract at: http://www.synopsys.com/Community/SNUG/India/Pages/Abstracts.aspx?loc=India&locy=2011#TA1

What: OVM/UVM paper with Intel-CVC-SNPS: http://www.synopsys.com/Community/SNUG/India/Pages/Abstracts.aspx?loc=India&locy=2011#TA1

When: Thursday June 23, 2011, 10.30 AM

Where: Leela Palace Hotel

What: Meet TeamCVC @ our booth, DCE: Win books, gifts, take quiz etc.

When: Thursday, June 23
Time: 5:15pm - 7:15pm
Location: Grand Ballroom, Leela Palace

Verification gets another buzzword - “ADS” thanks to Cadence

2011-06-16T12:16:00.001-07:00

At DAC 2011, Cadence introduced yet-another 3-letter buzzword to the wonderful world of Verification – ADS: Assertion-Driven Simulation. Traditionally assertions have been monitors/passive elements, but some high-end formal verification groups have been using it to drive model checkers, random stimulus generators etc. CVC (www.cvcblr.com) has a long history with assertions and we saw this ADS model first with a start-up named Safelogic in Sweden, that got acquired by Jasper a while ago. Under the hood most of the formal tools could do this – be it CDN’s IFV, SNPS’s Magellan etc.

Jasper rolled out ActiveDesign in 2010 and TeamCVC spoke to the developers and blogged it at http://www.cvcblr.com/blog/?p=132

Recently Zocalo (www.zocalo-tech.com) announced VisualSVA product that enables capturing of SVA via a GUI and also provide debug traces

And now Cadence brings it even more closer – down to your Simvision window – with a push of an additional button in your favorite Waveform window you get stimulus, see: http://bit.ly/mo9kjl

This is certainly encouraging and will propel the industry to increase the much needed assertion density among legacy & new RTL designs to improve the quality of designs.

From a language perspective SystemVerilog 2009 added checker..endchecker and rand variables inside. While the 2009 LRM limits the checker to be “monitors” alone, the recent discussions in the SV-AC IEEE extension groups proposals are emerging to make them “generate random stimulus” from checker blocks too. So stay tuned for more on ADS :-)

An evening full of Do’s & Don’ts in OVM/UVM with Cliff Cummings

2011-04-13T10:38:00.001-07:00

Clifford Cummings (http://www.linkedin.com/in/cliffcummings) is a crowd puller – no doubt. Consider:

Hot summer mid-day (2 PM start time)
Bangalore traffic/center of city (potential peak traffic towards end time of 5.30 PM)
A venue known/infamous for a “HUGE” area but no so frequented by hi-tech community of Silicon Valley of India, past events over there had history of terrible attendance

Yet there were close to 70+ Verification engineers at Cliff’s UVM/OVM seminar aptly titled as:

“Advanced SystemVerilog Tips Including OVM & UVM Tips”

It was indeed for Advanced System Verilog users as he had most of the slides on OVM/UVM. TeamCVC (http://in.linkedin.com/in/cvcblr) specifically its trainees, some 11 of them were there cherishing their stint at CVC (www.cvcblr.com) as they hear a world-class seminar and being a fresh graduate, making sense out of that was a pride on its own. That’s the power of CVC’s time proven EIC training (http://www.cvcblr.com/trng_profiles/CVC_EIC_profile.pdf) that takes in a fresh B.E/M.Tech graduate and turns them to be most sought out Verification engineer in local market.

Madhavi Rao of Cadence (http://in.linkedin.com/in/madhavirao) has done an excellent job in making the event popular and driving it to customers. TeamCVC did their bit, by blogging about it via: http://www.cvcblr.com/blog/?p=325 and also tweeted via: http://twitter.com/cvcblr – for those who believe (still) that Social Media is not engineers/hi-tech, there were more than 5 folks who told me at the event that they heard it via Tweets and they signed-in for the event!

Coming to the event technical content – A good detailed, 60-page write-up by Cliff is at: http://j.mp/gJegMP And for those who cherish/enjoy live-tweets, let’s not repeat all the hardwork TeamCVC had put in live-tweets during the event itself, see: http://twitter.com/cvcblr

The true success of the technical value was evident towards the end – during the High-Tea, almost every attendee had atleast one TIP to go home with (many with more than 1 obviously), I heard things like:

I would not use global_stop_request after run_test

I would not look at enable_stop_interrupt

etc.

Cliff cited JL Gray (http://www.linkedin.com/in/jlgray) for his interesting analogy of OVM’s TLM port-export to the famous Hollywood Blockbuster Avatar Movie. I am still looking for more details on that comparison as it wasn’t easy to catch that link during Cliff’s brief notes.

Cliff’s own explanation of port-export to a driving-a-car using steering-wheel was interesting as well.

Cliff’s session on handling end-of-test was the best pick in this event. Start with the following:

initial begin : end_of_test_try

run_test();

global_stop_request;

end : end_of_test_try

If you need more details, read: http://j.mp/gJegMP

It was indeed a nice evening with Cliff and other Verification geeks of Bangalore. Now, let’s look forward to how the Pune event goes, maybe http://twitter.com/punechips will provide us the live-tweets :-)

Spend 3 hours to know more about UVM, OVM with Cliff Cummings @ Bangalore/Pune

2011-04-06T11:04:00.001-07:00

If you are curious about recently released UVM standard – you won’t have missed to note the DVCon-2011 blogs/tweets etc. Some of those captures can be seen at http://www.cvcblr.com/blog/?p=283

http://www.cvcblr.com/blog/?p=298

http://www.cvcblr.com/blog/?p=322

Now, in case you didn’t visit DVCon, here is UVM coming to YOU – at Bangalore & Pune. Thanks to Cadence & QLogic, there are free UVM update events being scheduled on Apr 13th & Apr 19th. Register for free right away.

Agenda:

New UVM 1.0 overview and comparison to OVM
Important OVM and UVM phasing
Secrets in mastering OVM and UVM
Graceful termination of tests in OVM and UVM with emphasis on the objection mechanism
Some of Cliff's favorite SystemVerilog tips and tricks
Some early UVM techniques and best practices

Date

Time

Location

April 13, Wednesday

2.00pm – 5.30pm

Bangalore

Auditorium 1
NIMHANS Convention Centre
Hosur Road, Bangalore

April 19, Tuesday

4.00 – 7.30pm

Pune,

MCCIA Auditorium
A-Wing Ground Floor
MCCIA Trade Towers
(Building with Crossword Book Store)
Senapati Bapat Road, Pune

Pune – the “Oxford of the East”, SystemVerilog and the vibrant community

2011-04-03T12:00:00.001-07:00

Last week TeamCVC held a 4-day training on System Verilog at Pune – a pleasant city in the western ghats of India, also known as the "Oxford of the East" due to its vast student community & research institutions.

TeamCVC has been to Pune few years back for a VMM training, see some of those experiences at http://bit.ly/eHMaH7

But this visit has shown how fast this city has been growing and the recent boom it has been experiencing - atleast through an entrepreneur viewpoint. The first thing that struck me on my way to the hotel from airport was the flurry of developments – almost 90% of all hoarding/banners showing upcoming apartments, It is almost like Bangalore some 10 years back – with so many IT firms growing their staff strength, new office spaces being built etc.

The weather was pleasant, gets quite hot mid-day but then cool breeze in the evening, gets little cold during early mornings. Kind of similar to Bangalore, atleast for this period of the year.

The Hinjewadi area/IT park is amazingly clean, well maintained, with wide roads. Trafiic was sensible, a BIG sigh of relief for a Bangalorean :-) Though there are BPO vehicles plying along the roads, they are not as hars driving as their counterparts in Bangalore are.

Coming to the training folks, what really surprised me was the true cosmopolitan nature of the IT crowd there (from the general media projection of Maharashtra). There were folks from Andhra, Karnataka, Gujarat, Delhi and of-course Pune & around. The razor sharp audience kept the training truly interactive and alive. I generally have a higher image/perspective of Maharastrians when it comes to intellect and I wasn’t proven wrong, the audience were dot on time with labs, always had the enthusiasm for learning more – something that a passionate trainer would look forward to in each session. It is indeed a pleasure to have such attendees as connoisseur. It was a mix of few experienced folks and some fresh graduates, similar to our recent Cochin experience (Read: SystemVerilog Assertions Field-day). However, the biggest difference was that the attendees were finishing all labs on time and were asking for more stuff, pretty impressive talent pool indeed!

There were some good discussions around the SystemVerilog assertions – specifically on the Sequence repetition operators and the first_match. While we cover the basic repetition operators in our first session on sequences, we defer the first_match to advanced sequence session. One set of attendees finished the lab on sequences faster and started debate on "potential multiple matches" and the necessity of the consequent to hold for all matches. VCS DVE’s sequence debug/visualization came in very handy to appreciate the SVA behavior.

The discussion on $cast in SystemVerilog went on really nice, with new animation kicking in on demand and was well received. While the "syntax" was learnt the hard way, some folks weren't convinced on its real usage – not uncommon as the first level SystemVerilog course, we call it VSV () shows you how to use it, but our methodology sessions truly leverages it. Some of the tech-hungry attendees said "Yeah Dil Maange More.." and we quickly opened up $VCS_HOME/etc/rvm/vmm.sv and showed some of the real life usage of $cast – the instant reaction was "Oh My God – so common in reusable code.

Wanted to add more stuff, but realize it is already a long post, so perhaps some other time with few images to make it more interesting to read.

Powered by Qumana

What’s beyond UVM? - Excerpts from DVCon BoF panel

2011-03-11T19:05:00.001-08:00

Last week at DVCon we had a very interesting Birds-of-a-Feather meeting on Mar 1st evening. Panelists included Tom Anderson from Cadence, Yunshan Zhu from NextOp and Adnan Hamid from Breker Systems.

It was moderated by Srinivasan Venkataramanan from CVC. See pre-BoF invite/details at:

http://www.cvcblr.com/blog/?p=272

The theme of this panel was “Verification Closure” – given that 2011 DVCon marked the birth/release of UVM standard for developing reusable, inter-operable VIPs, it was a perfect fit for a group of technocrats to explore what is beyond UVM. We had some very interesting discussions and here are some excerpts. If you feel I missed some discussion topic or have any comment on this, feel free to blog it here!

To start with, Rick Nordin of Breker Systems introduced the panel topic and the moderator.

Srini (www.linkedin.com/in/svenka3) presented single slide setting the stage for the panelists and had the honor of introducing the esteemed panelists of the evening: Tom, Yunshan & Adnan.

Here is the slide from Srini:

Basically – we have the UVM now, how do we leverage and verify a complex SoC with it – what are the pieces of the puzzle involved beyond UVM itself? At broad level here are the key pieces:

Tests/Stimulus – co-ordinated across several UVM VIPs/interfaces – this is far beyond regular SystemVerilog constraints, UVM sequences. Sure UVM’s virtual sequences can help, but with lot of coding and very little reuse from block to SoC level, see http://www.cvcblr.com/blog/?p=272 for some example.
Targets/coverage goals – not just “code coverage” or “cross every possible input to every possible output” – rather “qualified”, identified and possibly filtered as per existing simulation runs – all automatic
A robust platform to do the execution, track it in an executable plan and measure the progress

Tom presented first with Cadence’s solution of automated constraint automation, vPlan and integrating adjacent technologies such as Formal, Emulation etc. He was as grand as ever in his vision and covered a whole lot in 1-slide indeed! Pircked it from Tom’s parallel blog on this topic: http://www.cadence.com/Community/blogs/fv/archive/2011/03/11/a-modest-proposal-using-formal-to-close-coverage-gaps.aspx

Then Yunshan presented how to automatically identify qualified coverage targets based on RTL + existing simulation run through NextOp’s Assertion Synthesis. This has caught lot of users excited about this technology and the emerging customer reports from companies like Altera (at deepchip.com) is only making the case more stronger! Here is a quick snapshot of what NextOp brings to the table in this space (from: http://www.nextopsoftware.com/Te_AssertionBasedVerification.html).

Yunshan also presented on how this fits nicely to today’s existing flows and extends the scope for formal/emulation on demand basis. This is extremely beneficial as the audience got to see that NextOp doesn’t really change the flow, rather fitst nicely to any existing flow and brings in value instantly.

Then it was Adnan’s turn to present his views and he started with a BANG! showing how “Model based stimulus-check-cover” generation helps in achieving Verification Closure. In his terms the “testcase generation” is incomplete if it talks “only” about the stimulus – instead it should capture the “stimulus, expect/checker and a coverage model” all in one. A grand idea in plan, call Breker to see how to make it true on your designs!

Then Adnan moved on to addressing the SoC level challenges in developing, C based tests with all desired bells-n-whistles such as:

Reuse of IP level scenarios/graphs
Automated C test generation
Heavy memory coherency and
Debug of such scenarios as-if it is plain SW code (via ubiquitous printf)

Perhaps too much to absorb in 10-minutes, but that’s why they had a booth at DVCon exhibit :-)

Then we had an exciting set of audience questions ranging from “explicit goals to hidden targets” (an interesting attendee posted it by taking examples from Hindu mythological characters such as Ravana & Indra – I will try and cover that in a separate blog on that for pleasure, if not anything else..). A quick summary of that question:

I am clear of an explicit goal to be hit by my SoC env (though it is not trivial to

hit it through simple set of “constrained random sequences” running on their

own, need a great deal of co-ordination).

But what about those “hidden/invisible” targets that are deeply buried inside

my huge RTL code base?

Ans: This is where "Assertion Synthesis” neatly plugs-in – given a set of simulation results, it goes into selected set of blocks/IPs, analyzes it and reports “quality properties” that the design + simulation exhibits. Now the user (typically the block owner) reviews those properties and marks these as assertions or cover holes. Sure there is work – but a targeted set of properties on potentially unstable/suspicious blocks/IPs with automated pruning of “redundant” stuff is a BIG deal indeed. Talk to www.nextopsoftware.com for more!

Some of the attendees:

There were some excited/over heated arguments about temporal properties vs. white-box ones, especially from Vibarajan (http://www.linkedin.com/pub/vibarajan-viswanathan/3/568/343P). The fact is existing System Verilog constructs do a great deal of work for block level/IP level properties, but they fail to deliver at SoC level of abstraction involving class based transaction level behaviors. Sure one can do lot of code around behavioral checkers/scoreboards (and as my good friend Nitin puts it – aren’t you trying to use wrong feature for wrong problem? – I respectfully disagree on this).

Another interesting discussion was around reach-ability of various cover goals. The panel seemed to have the best answers given the abundence of talent/experience on the panelists. Tom explained how formal analysis can either reach them – even if they are hard to reach via regular constrained random generation. Tom also pitched in the role of “unreacahbility analysis” as some of the goals might be just NO-GO given the design constraints/logic and it is very hard to identify them manually. When it comes to higher level, system level scenarios there is this new Graph based scenario models that can literally “mind-map” verification intent thereby letting users “begin-with-end” in mind. You need to listen to Adnan to believe it, or better yet evaluate their flow to benefit from it!

Photos from this BoF courtesy Joe Hupcey are at: http://www.flickr.com/photos/24605532@N08/sets/72157626233541664/with/5513590114/

If you have any more comments/questions to the panel, feel free to add them here in this blog (http://www.cvcblr.com/blog/?p=319) as comments, I will try and get the panelists respond.

Extracts from DVCon UVM poster session – it is vibrant ecosystem indeed

2011-03-04T23:37:00.001-08:00

Here are some snaps from recent DVCon UVM poster session. More than 12 vendors demonstrated their commerical offerings around UVM and it was an electrifying experience for the attendees/potential customers (some 180+ UVM tutorial attendees). Products/offerings broadly fell in the following categories:

Simulators – Cadence, Synopsys (DOn’t recall Mentor on poster, but of-course Questa supports UVM), another missing poster EDA tool company was Aldec. Though both Mentor & Aldec had their booths at the exhibit.

Cadence had a poster on how IUS supports UVM and extended debug features targeted for UVM users. Here is Joesph H with his Cadence poster

Synopsys had a clear, simple poster on how VCS extends its leadership in SystemVerilog performance. Here is Adiel Khan explaining with passion to a customer Synopsys poster:

Register model automation, maintenance: AgniSys dominated the poster with lots of visitors asking questions. Infact their poster attracted attendees even after the tutorial break was over and the session re-started. Alas, Anupam wasn’t there, but Srini from CVC (www.cvcblr.com) did some back-up for Anupam. Part of EDA ecosystem, Huh!

Here is Anupam explaining his poster to a customer potential:

Other similar offerings were demonstrated by Semifore & Doulog.

Trainings: Clearly attendees were well treated by thriving training ecosystem – with CVC (www.cvcblr.com), Doulos and others showing off their new trainings on UVM.

VIPs: CVC (www.cvcblr.com) launched its latest campaign around UVM aptly named “UnleashingUVM” with trainings, products & services around UVM.

Here is our CTO, Srini (http://www.linkedin.com/in/svenka3) with the poster:

And we had an interesting visitor all the way from home (Bangalore) – Mr. Amit Sharma :-)

Here is a more detailed list of CVC’s products & Services around UVM:

Overall it was a great successful poster session and the user interest around it is a standing testimonial to the overwhelming customer expectation on UVM.

Why UVM is important for the Semiconductor community?

2011-03-02T13:12:00.001-08:00

At DVCon Accellera released its latest standard for VIP interoperability named UVM – Universal Verification Methodology.

12+ vendors demonstrated their commercial solutions around UVM – hasn’t happened for a long time in the industry around single standard – except perhaps for SystemVerilog itself (back in 2003?)

While the technical details can be talked for very long time, here is a practical, real-life experience of “waiting for too long to have this standard”. This could be your simple means of convincing your technical management why they should be looking at UVM seriously in next project.

On the DVCon evening (Mar 1st) I was having dinner with a good old friend of mine, Mahesh. Here are his experiences/pains of working with various verification projects for the past 6+ years:

Mahesh –

it was a nightmare 5-6 years ago for Verification engineers – you move from one project to another within the SAME company (for instance acquired companies in a large company), your way of work – a la - “methodology” changes, hell! How I write my BFM, how it interacts with rest of the environment, how do I control my number-of-transactions etc. etc.

And when you switch jobs – almost guaranteed to go through the unlearn-learn cycle. While this cycle is good in many-a-context, but not to do the same thing – in this case “verification” – just with different base classes/languages.

He was listing: e, OpenVera, SystemVerilog languages and eRM, RVM, VMM, AVM and the likes..include OVM if you move the timeline little closer to 2011 :-)

So having a standard methodology is certainly promising for end users and for management to manage resources across projects. Sure there are more compelling technical reasons too – hopefully all for better, but the good things is, even if there are some shortcomings, it is a platform to add things to and bring it to Accellera to grow it beyond UVM 1.0.

Here is a snapshot of what CVC (www.cvcblr.com) has to offer for you around UVM – UnleashingUVM

Explore technologies for “Verification Closure” at DVCon BoF meeting, Tuesday Mar 1st 6.30 PM (PST)

2011-02-27T22:42:00.001-08:00

Big picture – Verification Closure

Panel members: Cadence, NextOp, Breker & CVC

If you are attending DVCon starting tomorrow, here is a panel that you may not want to skip – yes UVM is hot and ready-to-go. How do we leverage that and get to faster Verification Closure – that’s precisely what we will be discussing in this “Birds-of-a-Feather” panel at DVCon www.dvcon.org on Tuesday Mar 1st, 6.30 PM US/Pacific time at Donner Ballroom, DoubleTree Hotel, San Jose.

Here is a summary of what to expect in this panel discussion:

UVM is great! Enables interoperable VIPs to be created, reused. In a typical SoC – several such UVM VIPs get integrated and 1 (or more) embedded processors (ARM-like) configure/control the flow. Individual sequences/virtual sequences at UVM level will do great for peripheral-alone testing.

Taking right from UVM SoC reference flow @ www.uvmworld.org, here is a sample SOC:

How about true “flow/scenario” testing? UVM’s virtual sequencer is “A possibility”. A pragmatic approach as outlined by an excellent article by my good friends @ Applied Micro, Pune (India) is here:

http://www.design-reuse.com/articles/22264/system-verilog-ovm-verification-reusability.html

The above approach requires lot of coding, synchronization and pretty much directed across transactions/interfaces. How do we randomize “across interfaces/peripherals” to mimic system-level flows/scenarios?

Even if we code up all Sequence libraries, virtual sequences and virtual sequencers – we got only the stimulus, what about complete “Verification Closure”?

On top, overlay Low Power features, requirements and annotate Power State table information – the number of different paths/arcs to be coded and tested is mind boggling – imagine coding them via virtual sequences/sequencer – do-able, but lot of work indeed!

Every DV team does this today in one-way or the-other. But what new technologies are available or becoming available to assist?

Come and listen to experts in this domain at “Birds-of-a-Feather” panel at DVCon www.dvcon.org on Tuesday Mar 1st, 6.30 PM US/Pacific time at Donner Ballroom, DoubleTree Hotel, San Jose.

Here are some key items that would be discussed: If you have more ideas/questions send them across to sevnka3@gmail.com or post as additional comments here at www.cvcblr.com/blog I will incorporate them as much as I can!

Need truly inter-operable VIPs to start with – This is where UVM comes-in. We at CVC are at DVCOn UVM poster session.
Need key “metrics” to define, drive and track the progress (Various sources including formal)
How to focus on “critical, high quality” coverage targets?
A coherent, high-level mechanism to capture the scenario models that aid in:

generate stimulus
capture scenario specific checks/criteria for success and
Cover them across interfaces, temporal transaction coverage

Come and share your views, learn what your fellow DV folks do all at DVCon!

Feedback from customer on our SystemVerilog training

2011-02-07T10:09:00.001-08:00

Recently TeamCVC (http://in.linkedin.com/in/cvcblr) conducted a 4-day SystemVerilog workshop at Kochi, South India. Some musings at:

http://www.cvcblr.com/blog/?p=259

And today we received a cool note from customer voluntarily:

Vinayaraj T R, Project Engineer @Cochin:

I have attended your training on System Verilog for Verification conducted last week at Kochi. The session was very much helpful for me and even being a fresher I was able to understand the concepts and gain a lot of knowledge from it. I am very sure that it will help me a lot through out my career.

It would be helpful if you could share the lab tutorials of that training.

Thank you once again.

Regards,

Vinayaraj T R,

Vinayaraj is certainly not alone. It is this customer satisfaction that gives us the “passion” to do more!

Until another customer success story, it is sign-off from Bangalore, TeamCVC

Find deeply buried functional bugs with Graph based solver

2011-02-07T09:15:00.001-08:00

Are you an expert Verification engineer using upto date languages & methodologies available such as Specman/E, SystemVerilog, VMM, OVM, UVM etc.? Are you looking for even more technologies to find “deeply buried functional bugs” in a language agnostic manner, yet be able to reuse the underlying TB code? Read what Dave Whipp, a veteran HW Verification engineer found working over the last few years:

http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=4172

Specifically:

There is a pressing need for testing tools that are language-agnostic – and such tools are indeed emerging. The shadow of the SystemVerilog steamroller is lifting.
One such tool, that I have been using successfully over the past few years, is Breker’s Trek. Trek randomly generates directed tests using a constrained random walk of a graph (constructed by verification engineers) that describes how an environment interacts with the DUT. This is a step back from the purist approach of SAT-based constraint solvers, but it does provide an effective platform for exploring deep sequences of interactions. It would be good to see panel discussions of SAT-solving Vs graph walking as methodologies for finding deep bugs.

See a snapshot of how a graph based solver can explore constraints that maybe “temporal” and across several transaction hierarchies:

There is lot more to Trek than this, but this ability itself is beyond today’s existing SAT based solvers. Now combine that with the STRONG and UNIQUE block-to-SoC auto test generation – a new paradigm in verification is rolling out..

See www.brekersystems.com for more. And CVC (www.cvcblr.com) is your partner in India to bring this advanced technology close to you, call us if you want to learn more.

Happy testing!

SystemVerilog Assertions’ field-day at Port city of Cochin!

2011-02-01T09:26:00.001-08:00

TeamCVC (http://in.linkedin.com/in/cvcblr) is at Cochin, a famous port-city in South India (http://en.wikipedia.org/wiki/Kochi) this week on a “Mission SystemVerilog” at a customer site. It is a 4-day program covering:

SystemVerilog basics for RTL designers (http://www.cvcblr.com/trng_profiles/CVC_LG_SVD_profile.pdf)
System Verilog Assertions (http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf)
SystemVerilog for Verification engineers (VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf)

The audience is a mix of young, enthusiastic engineers in their early-to-mid career – all very keen to hone their skills on SystemVerilog. Our CTO, Srini (http://in.linkedin.com/in/svenka3) chose to customize the training in a timely manner to get the audience involved and interactive. During Day-2, it was a true “field-day of SystemVerilog Assertions”. Especially when it came to Sequence repetition operators, it was fun all across the room. Needless to say CVC’s SystemVerilog Assertions labs are very well laid out with concrete examples to demonstrate the various sequence operators. However with assertions the fun really lies when you “slightly” change the sequence and/or the trace. Here are some screenshots from this “field-day”.

One of the sequences that we experimented is to demonstrate the difference bet’n non-consecutive [= N] & GOTO [-> N] operator.

One of their smart engineers asked/wanted to change the ##1 to ##0. This is to explain the “endpoint” of a sequence/property as in:

a |=> b [-> 2] ##1 c;

Lucky that we had access to Riviera-Pro running on our laptop, on-the-fly we could tweak the code/trace and demo it live:

The fun gets only more when there are multiple threads & multiple attempts. Here is how Riviera-Pro nicely shows it up on Waveform – like a real “THREAD”.

TechnoFun with System Verilog – I turned rand_mode OFF, yet get constraint violation? Crazy Friday evening phenomenon, maybe?

2011-01-21T08:21:00.001-08:00

Ravi Teja , ASIC Design-Verification Engineer @ www.cvcblr.com &

TeamCVC (Nikhil, Satish, Srini et al.)

SystemVerilog is a massive language with several surprises under its belt. Every time you encounter some unexpected result, the first reaction is “Oh! I know System Verilog, this is incorrect behavior of the tool”. Voila! EDA developers get paid *really well* and read the LRM thoroughly before committing their code in. This is not to say that there are no bugs in EDA tools (“bug free EDA tool” is more or less an OXYMORON). But with System Verilog tools becoming more and more stable and advanced, it is very likely the case that you fall under the famous John Cooley’s signature (www.deepchip.com):

So was our recent experience with Aldec’s Riviera-Pro simulator with SystemVerilog constraints.

Let the code speak for itself:

class xactn;
   rand int var1;
   rand int var2;
   constraint c_var1 { var1 inside {[1:10]};}
   constraint c_var2 { var2 inside {[1:10]};}
endclass:xactn

Now var1 & var2 are non-state variables. Whenever I randomize an object of this class, the solver should obey the constraints – no ground breaking stuff, is it? Consider turning the non-state variables to “inactive” state. SystemVerilog supports rand_mode(0/1) for this, a quick explanation for the same is below:

Now the real fun starts when you delve into corner cases (a la “the devil lies in the detail”). Even though the rand variable is turned inactive, its value MUST be within the values as demanded by the constraints – in other words the “constraints” are still ACTIVE. This has obvious but overlooked results when used with a rand_mode(ON/OFF). The results after randomization are tabulated below:

So why is the 2nd & 3rd case don’t result in random values for var2, var1 respectively? Isn’t that a bug in the EDA tool? Shouldn’t we be calling their support@aldec.com staff? Hold on.. Let’s believe the tool, after all – some of the best minds in comp-science write these geeky solvers, they must have had something in their mind while writing this piece of code inside :-)

A little bit of RTFM (Read The Fine Manual) reveals the “hidden” secrets of “Art of Debug” with Riviera-Pro. It supports a rc_verbose flag which, when set to a magic value of “2” throws out messages to the log file.

set rc_verbose 2

# RCKERNEL: Error: ../src/test.sv(1): The condition 'c_var1()&&c_var2()&&rc_ext_constraint' is overconstrained.

# KERNEL: 1 (0,0) Var1 =           0 , Var2 =           0

# RCKERNEL: Error: ../src/test.sv(1): The condition 'c_var1()&&c_var2()&&rc_ext_constraint' is overconstrained.

# KERNEL: 2 (0,1) Var1 =           0 , Var2 =           0

# RCKERNEL: Error: ../src/test.sv(1): The condition 'c_var1()&&c_var2()&&rc_ext_constraint' is overconstrained.

# KERNEL: 3 (1,0) Var1 =           0 , Var2 =           0

# KERNEL: 4 (1,1) Var1 =           3 , Var2 =           9

# KERNEL: 5 (0,0) Var1 =           3 , Var2 =           9

# KERNEL: 6 (0,1) Var1 =           3 , Var2 =           4

So the first 3 randomize() calls were failing – important that you handle the return value from object.randomize() (Guideline-1).

First three cases gave a constraint violation. We observed that for cases 1,2,3 atleast one of the constraints is not fulfilled.Hence the randomize method returns zero. What? I turned the rand_mode to OFF, yet it tries randomizing and failing? Crazy Friday Phenomenon Huh?

Oh Dear, wait..let’s peel the onion and see why..

This is because each call to randomize involves two steps:
1)solve
In this step all the constraints are solved (as they are still active). The solver must keep the values of var1 and var2
between 1 to 10. Their default values are however 0. (i.e var1=0 & var2=0) . This violates the constraints, hence the solver failed.
2)assign
If the solver passed (i.e no constraint violation) and rand_mode is ON then the randomized value is assigned to the variables

Now in case 2 & 3 wherein only one of the variables is set to rand_mode(OFF), the AND operation means that – since the solver ahs failed, no assignment of potential random value to the other variable is performed, hence retaining the value 0f “0”.

Now, the constraint debugger with Riviera-Pro is good to start with, wish it had pin-pointed it to the exact constraint that caused the violation, instead of combining both into single equation as:

# RCKERNEL: Error: ../src/test.sv(1): The condition 'c_var1()&&c_var2()&&rc_ext_constraint' is overconstrained.

Oh, let’s leave some room for improvement :-)

Now, as a closing remark and 2nd coding guideline – if you are changing the rand_mode, see if you can isolate related constraint on that variable and make constraint_mode(OFF) as well. Once again as John Colley puts it:

From a fresh grad to VLSI Design engineer – Meet Mr. Kaleem, Sasken

2011-01-16T22:11:00.001-08:00

They say the best appreciation one can get is through one’s customers’ voice – we at CVC (www.cvcblr.com) take every individual trainee as serious as our corporate customers. That has been our reason behind success on both Corporate & individual levels. Here is yet another success story, this time from Md. Kaleem, ASIC Design-Verification Engineer @ Sasken. Kaleem got trained by TeamCVC and also was consulting for us for 2 projects after the training, through which he gained real practical knowledge that has helped him sail through the tough job climate. Kaleem went through our EIC (http://www.cvcblr.com/trng_profiles/CVC_EIC_profile.pdf) and then worked on OVM http://www.cvcblr.com/trng_profiles/CVC_DR_OVM_profile.pdf projects before moving on to even better job prospects.

Here is what he wrote to us over this weekend! Good luck Kaleem and keep in touch!

Mohammed Kaleemulla (http://in.linkedin.com/pub/mohammed-kaleemulla/23/186/b98)

Sent: Sunday, January 16, 2011 12:23 PM

Hi,

Sir This is Kaleem here,i have got a job in Sasken for the post of design verification engineer,I thank CVC for giving me all the support required for developing the technical and knowledge-able skills, without which I wouldn't have reached here and I hope we will have a reciprocate communication.

Regards
Kaleem

SystemVerilog constraints – distribution & using FCOV to visualize the effect

2011-01-16T19:18:00.001-08:00

– Satish U, ASIC Design & Verification engineer @ CVC (www.cvcblr.com)

Every day at work is learning something new. More so when you are asked to work deep into advanced technologies such as SystemVerilog. In a recent project I was asked to delve deep into the constraints portion of SystemVerilog and solve few customer problems in modeling real life traffic pattern generation using SystemVerilog constraints. As part of it, I came up with an interesting to way to visualize the distribution through SystemVerilog covergroup/coverpoint. Though it is little round-about and may not be the best way to “verify” distribution, the technical lead at CVC quickly grasped the value and encouraged to explore more and develop a blog on the same. It is this “cultivating ideas” that makes working at CVC (www.cvcblr.com) a perfect blend of learning & fun (and don’t miss it – very aggressive timelines too).

A New way to check the distribution

By definition the distribution within randc must be uniform. Let’s formulate this statement and validate the same. To find the distribution of lets say randc within a particular range N (N is the number of values in the range). Now let us assume M is the number of times an object is randomized.

Each value has a probability of 1/N.

Case1: IF M = 1*N - If M= N then the values should be unique without any repetition.
Case2: If M = 2*N - each value should be generated 2 times.
Case3: M = K*N. Hence the number of times each value shall be generated is equal to K.

The N & M determine the “stimulus” side of verification. How do you “check” the distribution? An automated & robust method would be to use a queue and check the contents of the queue to see if they are unique, Infact one of our interns (Suhas: http://in.linkedin.com/pub/suhas-reddy/15/b02/49) is doing this as a mini-project at CVC (www.cvcblr.com) as part of our popular BUDS internship (http://www.cvcblr.com/downloads/BUDs_CVC_Acad.pdf).

However I proposed another interesting way to do this: Declare X as a cover point within a covergroup , so by default we will have N bins created for the N number of values (else one could use the auto_bin_max if care to). Other choice would be to use an array bin as shown below.

To demonstrate with an example:

`define N 4

`define K 1
`define M `K ** `N

`define seed_value 100

package pkg;
class xactn;
randc bit [(`N-1):0] a;

covergroup cg;
   A_cp      : coverpoint a { bins a[] = {[0:15]};}
endgroup:cg
   function void post_randomize;
     cg.sample();
   endfunction

lets assume a 4 bit vector a, So we can have 16 possible values (N = 16).

We used Aldec’s (www.aldec.com) Riviera-Pro:

Here is how Riviera visualizes it in its coverage report.

Case1: for M = N if all the bins are hit once it means that i have uniform distribution.
Case2: M = 2 * N - each bin should be hit 2 times.
Case3: Now lets take the constant 2 as K. the equation becomes M = K*N. Hence the number of times each bin is hit will
be equal to K.

We used this method to analyze various constraints and distributions. More about it in part-2 of this blog. Stay tuned to VoW blog!

Mentor’s User-2-User conf is nearing – have your Qs answered through John Cooley!

2010-11-30T00:23:00.001-08:00

If you haven’t registered yet, goto:

http://user2user.mentor.com/bangalore-india-2010.html

With Wally Rhines speaking, you can’t afford to miss his power-packed keyonte. Also this year there is Mr. John Colley of www.deepchip.com presenting a session. Known for his open, user-focused comments on various tools, technologies & vendors (sometimes creating controversies too) this is one session that’s worth beating Bangalore traffic to be there!

BTW, John is also looking for good survey questions focused on Indian audience and issues concerning Indian users of Mentor tools. So do send them across via www.deepchip.com

See you there at Mentor’s U2U on Dec 10th. Look for TeamCVC (www.cvcblr.com) in the crowd and we can chat!

TeamCVC,

www.cvcblr.com/blog

Increased user momentum at CDNLive India

2010-11-19T11:29:00.001-08:00

Quick summary of what I liked at recent CDNLive India. Read live tweets @ www.twitter.com/cvcblr

First of all, the venue is FRESH – ITC Royal Gardenia hotel, a welcome change from regular Leela/Taj :-) Second, the first few sessions were JAM-packed with more than 25 customers standing (with all seats occupied). This was surprising as the audience beta the Bangalore traffic to be there at around 9.30 AM.

On the technical front, well let’s focus on what we know best – Front-end Design & Verification. Frankly – I was not alone who got totally confused about which “Verification” track to choose from. There was this

“FED + Verification track”
System Design & Verification track

I first though it was the FED that I should be in, as it contained one of my much awaited Nokia paper on Formal/ABV/IFV usage. But my good friend @CDN Maruthi Srinivas helped with clarification. His explanation:

First of all sorry for confusion, this year we had so many good papers on Verification and we had to fit as many as we can. We decided to move some of the Formal/ABV papers to FED track. The core Verification papers are on the Track-V

Now being @ the common session, John Bruggeman did an excellent job with his EDA360 talk. With so much being tweeted about it, honestly I got little saturated prior to his talk. But his talk truly rejuvenated the topic and his expressive demo revealed the vision well inside 3 slides. Kudos JohnB!

Next to see was TomAnderson’s Verification roadmap – strangely this was presented at Track-IV/FED. Luckily I was there in that track and as ever before, Cadence’s vision was great – especially linking the Conformal LP and Functional Verification/MDV is very thought provoking. The “Advanced Specman” was known to us at CVC http://www.cvcblr.com/blog/?p=173, but for many it was new there. And with similar capabilities being explored for SystemVerilog in the roadmap, there was enough for everyone to cheer about!

On the technical papers – a noted aspect that almost every attendee shared is – the quality and depth of these papers this time around was amazing. Be it the DFT Verif paper from TI (90 % of DFT logic bugs were caught by IFV flow), the TLM-e paper from ST-Micro and/or the Arch Model Verif with Specman by TI.

I personally enjoyed the Freescale paper on “Corner Case analysis with Formal”, to avoid repeating it, read more about it at: http://www.cvcblr.com/blog/?p=215

Nokia’s Modem IP Verif paper was one of the best presented ones IMHO and Manish Goel did an excellent & upto-the point job of staying on target. There were enough audience questions in his session than many others and even another presenter from TI (He got the best paper award, didn’t get his name though) shared some of his views during those interactive discussions. This I felt was true “customer-2-customer” interaction happening live before a full room audience – something that the CDNLive team can be very happy about.

One of the best audience Q was raised during an Assertion paper (guess the TI one):

“While IFV sounds great, user still needs to write those white-box assertions, is there any automation available”?

Though the presenter didn’t use this specific feature, the CDN rep/AE was quick to note that indeed IFV has the ability to extract certain classes of properties from RTL.

..and for those looking for more quality assertions, explore the partner technology of BugScope from NextOp: www.nextopsoftware.com

Realities of IP reuse, from Verification perspective

2010-11-19T10:54:00.001-08:00

IP reuse, RTL/Design IP-reuse to be precise has been in effect for over a decade now, thanks to the time-tested RMM book, http://amzn.to/bI04yK and the extensive support of those rules/guidelines/policies by Lint tools such as SpyGlass, ALINT (from www.aldec.com), and recently Ascent (from www.realintent.com).

However while talking to a customer recently on their Printer SoC verification challenges, some interesting facts/stats emerged:

Yes we reuse IPs, they are Si-proven, but…

New SoCs use these IPs in very different context leading to:

Different configurations that were never used/tested/verified before
Order of configuring these IPs can make-or-break the systems

The “ordering” was more interesting and in recently concluded CDNLive India, Deeapk from Freescale Noida presented an excellent paper on: “Corner Case Verification with IFV and assertions”. While much has been blogged about the recently concluded event CDNLive, this paper didn’t get enough mention – atleast not as much as it deserves IMHO. Deepak had 3 excellent case studies:

Order in which IPs get configured can make-or-break the SoC. Traditional Code cov can not locate it. His team wrote those assertions manually and used IFV to verify them
During Power Shutdwon if there is a pending interrupt to be serviced, after wake-up that interrupt was forgotten – a pretty tall order for traditional code-cov to catch it. True one could write a test – only if you had thought about it!
Clock control from PLL and other enables

All these are quality bugs, but hidden in the given module for more than 1 tapeout and used in customer designs. They get exposed only with modern use scenarios and hence is the stress on increased quality, hence the need for IFV.

While Deepak’s team has successfully demo-ed the 3 corner cases, arriving at them was by no means a small task. Also who knows, how many such hidden gems/bugs are out there yet to be caught?

So while IP reuse sounds old, the verification of them is by no means is a done-deal. Great for WE all – those love Verification as it presents a good challenge.

Now just before I close this entry, a quick preview of an emerging technology that is well poised to change this scenario for sure – by generating QUALITY white-box assertions automatically for YOUR designs:

Looking beyond the current tools, emerging technology such as BugScope from NextOp (www.nextopsoftware.com) can greatly assist in identifying such corners from your RTL design and current simulation runs. You just need to see a demo/webinar or read carefully their Whitepaper http://www.nextopsoftware.com/assertion-synthesis-assertion-based-verification-whitepaper.html to explore more.

Leveraging Social Media in VLSI/Semiconductor/EDA – the ecosystem way

2010-11-19T10:14:00.001-08:00

As recent EDAC panel discussed the impact of Social Media in VLSI/EDA marketing (see: http://bit.ly/dzd3Ev) it is quite clear that one alone can’t make a difference, no matter how loud you shout – it is the collective ecosystem – of company-customers-partners that can make a win-win case in this new age marketing. Refer to Altera’s slide on that from http://bit.ly/dzd3Ev

Jim @ Altera says that it is the customer-to-customer interaction happening via Social Media that makes the bigger impact.

Given the post-recession ramp-up at many semiconductor houses, teams are very selective in investing/exploring/adopting new technologies and they are all looking for true success stories and real user views than just tool/feature updates.

Now looking at Karen @Synopsys’s views: it is the GEEK-2-Geek connection that she/Synopsys is bullish about to leverage on this new media.

While she quotes SNUG group @ linkedin.com, we found even more interesting stats with Verification specific groups such as VMM, OVM & all new UVM. The interesting fact about VMM linkedIn group is it is created and managed by partner (Ajeetha Kumari, http://www.linkedin.com/in/ajeetha) than the vendor.

VMM: http://www.linkedin.com/groups?home=&gid=147448 with some 780 members,

OVM: http://www.linkedin.com/groups?home=&gid=145498 with 1200+ members:

And the all new UVM: http://www.linkedin.com/groups?home=&gid=3092645 with 250+ members.

What really is important about this UVM group is it truly represents the ecosystem – with members from all EDA Vendors, partners and growing user base. See for yourself from the image below:

Another partner promoted group is SystemVerilog for Verification @ http://www.linkedin.com/groups?home=&gid=1924084

Among these groups the number of jobs being discussed truly reflects the close relevance of these to the real engineers out there and it is quite clear that all have enough to benefit from it.

So let’s embrace the new Social Media and look forward to exciting times ahead. If you want to learn more about how companies can benefit from this Social Media, do not miss the latest edition of Entrepreneur magazine in India http://entrepreneurindia.in/ – it has cover story on Facebook founder.

And here are some of our local enthusiastic bloggers/tweeters – am sure I have missed several, feel free to submit them as comments, I will add them to this ever growing list!

http://www.twitter.com/cvcblr

http://www.twitter.com/pradeep612

http://www.twitter.com/sricvc

http://www.twitter.com/am_its

http://www.twitter.com/testbench_in

http://www.twitter.com/punechips

SystemVerilog Assertions for VHDL

2010-11-17T11:21:00.001-08:00

It is becoming more and more popular to find users writing SVA for VHDL too – though the VHDL-2008 has PSL inside it and most of the EDA tools (Aldec, Cadence, Mentor & Synopsys) have good support for PSL-VHDL.

Recently a customer asked:

"The SVA binding port mismatch error only when I bind an VHDL output port to a SVA input port. But, when i bind a Verilog output port to a SVA input port, it compiles without a problem ".

While it does look like a tool-specific issue, in old VHDL, an output port can’t be read, need a buffer type for the same. When you bind a SVA to a VHDL output port, SVA tries to “read” it.

It is a subtle issue – though many tools have relaxed this “semantic” check on VHDL side. Also VHDL-2008 allows reading of output ports IIRC. Check with your EDA vendor if you see this issue, they ought to be supporting it already!

Cheers

TeamCVC

www.cvcblr.com

Productivity hint for SystemVerilog VMM/OVM/UVM users

2010-11-17T11:04:00.001-08:00

Whichever methodology you use for Verification (if you don’t use, better start with UVM maybe) – some of the tasks & requirements are common. One of them is the ability to control certain simulation features across runs without needing to recompile. Classicial examples are:

Dumping different scopes
Changing Verbosity (for debug, regression runs etc.)
Choosing tests
Stopping after N-number of errors

It is the last one that one of our customers recently had an issue with, here is an extract from his email:

I need clarification regarding "vmm_log:stop_after_n_error". Want to know
whether there is command line equivalent of the same.
I do not want to edit any of the source file but rather control from the command
line. Does the language/methodology has in built construct for the same ?

Interestingly an OVM user also asked for it during our recent OVM training (www.cvcblr.com/trainings) at their site. In OVM it is “max_quit_count”. In both cases unfortunately it is not built-in. This means that one needs to add it in source-code – something that we discourage to do. Instead build it using Verilog’s $value$plusargs, code snippet:

if ($value$plusargs("vmm_stop_after_n_errors+%d", err_count)) begin
log.stop_after_n_errors(err_count)

Guess that gives the idea, let me know if you are still stuck, send me
a working code/example, I will get that turned around quickly.

Regards

TeamCVC

www.cvcblr.com

SystemVerilog OVM’s apply_config_settings – why & were?

2010-07-02T10:02:00.001-07:00

Arayik Babayan, a friend of mine from Armenia asked me what is the use of “apply_config_settings” in OVM. As you may be aware SystemVerilog is a flexible language that can be used for building highly configurable and scalable verification environments. OVM adds a great deal of capabilities on top of plain “system verilog” to make it lot easier to handle that task. One of them is the configuration interface mechanism – usually we use set_config* and get_config* stuff. Internally OVM’s build() takes care of “applying” these settings. automatically usually. What if you want to change few settings across the env after the build? That’s when you use this apply_config_settings explicitly – it internally calls the set_*local for modified settings and viola – you are ready to go!

That’s “advanced OVM” for this week!

Enjoy OVMing..

TeamCVC

www.cvcblr.com/blog

Dealing with SystemVerilog constraint solver failures – the Questa way

2010-06-29T09:26:00.001-07:00

… Tuesday Technote on Solver Debug, Jijo PS, Srini TeamCVC www.cvcblr.com

Dealing with simple solver failure – looking for really “quick help”. It is a layered SystemVerilog code for a SAN Router. An inherited constraint in a testcase showed randomize() failure. Before you jump to conclusion on the simple nature of the problem – consider that this is the first time eevr I look at this design/env as the original author moved out of the company (sign of good times :-) ?) and am given to fix the code ASAP – in next 15 minutes that’s (sounds way too familiar, Huh?).

# Number of fware xactn 19
# ** Fatal: [Time 0 ns] Test cfg Solver failure
#    Time: 0 ns Scope: san_rt_top.san_rt_test_pgm_0.b1.lp.a1 File: ../
rt_test_03.sv Line: 83
# ** Note: Data structure takes 9699728 bytes of memory
#          Process time 0.03 seconds
#          $finish    : ../test/san_rt_test_03.sv(83)
#    Time: 0 ns Iteration: 2 Instance: /san_rt_top/san_rt_test_pgm_0

So what next? Consult our friendly Questa SolveDebug: add vsim –solvedebug and bang you go…

It does 2 things:

It prints the minimal set of conflicting constraints,
Creates a stand-alone test to reproduce the failure in a crisp testcase. See below:

Minimal set of constraints from user-code

# ../test/san_rt_test_03.sv(82): randomize() failed due to conflicts between the following constraints:
#     ../test/san_rt_test_03.sv(59): san_rt_test_cfg_0.cst_reasonable_fw_xactns_1 { (san_rt_test_cfg_0.no_of_fware_xactions > 32'h00001360); }
#     ../src/san_rt_fware_gen.sv(42): san_rt_test_cfg_0.cst_reasonable_fw_xactns { (san_rt_test_cfg_0.no_of_fware_xactions < 32'h00000032); }
# ** Fatal: [Time 0 ns] Test cfg Solver failure
#    Time: 0 ns Scope: san_rt_top.san_rt_test_pgm_0.b1.lp.a1 File: ../test/san_rt_test_03.sv Line: 83
# ** Note: Data structure takes 9699728 bytes of memory
#          Process time 0.02 seconds
#          $finish    : ../test/san_rt_test_03.sv(83

Testcase being created by Questa (system verilog code, can be run standalone)

# ../test/san_rt_test_03.sv(82): randomize() failed; generating simplified testcase scenario...
# ----- begin testcase -----
# module top;
#
# class TFoo;
#     rand bit [15:0] \san_rt_test_cfg_0.no_of_fware_xactions ;
#     constraint all_constraints {
#         // ../src/san_rt_fware_gen.sv(42): san_rt_test_cfg_0.cst_reasonable_fw_xactns { (san_rt_test_cfg_0.no_of_fware_xactions < 32'h00000032); }
#         (\san_rt_test_cfg_0.no_of_fware_xactions < 32'h00000032);
#         // ../test/san_rt_test_03.sv(62): san_rt_test_cfg_0.small_tst_cst { (san_rt_test_cfg_0.no_of_fware_xactions < 32'h000013ec); }
#         (\san_rt_test_cfg_0.no_of_fware_xactions < 32'h000013ec);
#         // ../test/san_rt_test_03.sv(59): san_rt_test_cfg_0.cst_reasonable_fw_xactns_1 { (san_rt_test_cfg_0.no_of_fware_xactions > 32'h00001360); }
#         (\san_rt_test_cfg_0.no_of_fware_xactions > 32'h00001360);
#     }
# endclass
#
# TFoo f = new;
# int status;
#
# initial begin
#     status = f.randomize();
#     $display(status);
# end
#
# endmodule
# ----- end testcase -----
#

Now that was easy to fix, simply override the test-specific constraint in the inherited test_cfg than “adding to it”. Glad I met my deadline for today!

Hats off Questa – wish it prints the vsim –solvefaildebug automatically on such failures to log file.

TeamCVC

www.cvcblr.com/blog

Pre-DAC round-up of Verification technologies

2010-06-07T02:41:00.001-07:00

Given the business climate and local commitments, it is hard for me to be at DAC. But with keen focus on Verification it is kind of important for CVC (www.cvcblr.com) to share our thoughts on fresh ideas/technologies on Verification that are being demo-ed at DAC-2010 (www.dac.com). Leaving the BIG-3 out (I hope to blog about them prior to DAC on what we see as “updates” from them separately), here is a quick round-up of what we see as promising solutions that any DAC attendee in Verification domain might be interested. Feel free to comment via our blog @ www.cvcblr.com/blog – we would love to hear them!

NextOP

One of the most promising start-ups in the assertion based verification domain. They have been in stealth mode for a few years. Only recently quite a bit of information has been let out about their technology. It all started with an eval report from a real user and active follow-ups from then – see: http://www.cvcblr.com/blog/?p=147

Ben Cohen (www.systemverilog.us) recently had some good discussions about this technology based on our DVCon-2010 paper on SVA paper (contact us to get a copy: http://www.cvcblr.com/about_us) It did find some interesting bug via simulation run –> property extraction –> coverage hole –> bug! It is a little long route, but however it is an interesting approach. See details at:http://www.cvcblr.com/blog/?p=163

Make sure you visit their booth @DAC (NextOp exhibits at Booth #1442) to learn more. In a nutshell their technology is about analyzing existing RTL & testbench+testcase (via regression) and extract quality properties for your design – then it is upto the RTL designers to qualify whether these “properties” are assertions/coverage/don’t cares. Their promise is minimal noise, but your mileage may vary!

Vennsa’s OnPoint

If you ask anyone in EDA/Semiconductor industry about the “elephant in the room” problem in front-end VLSI, the answer is loud-n-clear DEBUG! Besides SpringSoft/Novas noone seemed to have the perseverance needed to sail through tough times trying to address that problem. (Remember Veritools, anyone BTW?) Now we have a genuine attempt to automate the debug – Vennsa’s OnPoint. Not much is known yet about it, but here is a picture (Copyright by Vennsa http://www.vennsa.com/ ):

This actually fits very nicely with our Unique workshop on “Debug” (see: www.cvcblr.com/trainings) – wherein we look at some of the common debug problems and demonstrate how little tricks with TCL, GUI/Markers etc. can save you hours if not days!

Look at some of our earlier Tweet’s on OnPoint at www.twitter.com/sricvc to get some more info.

I’m sure we will hear more about it in coming weeks/months.

Jasper’s ActiveDesign

One of the most charismatic EDA tools that I’ve come across with so far – that’s if they really deliver on being the “Twitter of RTL Design” expectation that has been set of this. A picture is worth more than…here you go:

Read more about it at: http://www.cvcblr.com/blog/?p=144

Zocalo-tech

Do you care to approach your ABV adoption more methodically? Quoting Harry Foster, all time ABV promoter: (from his invited tutorial entited: “Assertion-Based Verification: Industry Myths to Realities”,

……”what differentiates a successful team from an unsuccessful team is process and adoption of new verification methods. Unsuccessful teams tend to approach development in an ad hoc fashion, while successful teams employ a more mature level of methodology that is systematic”. ……

Now Zocalo is one vendor trying to address that “methodology” aspect of ABV – via their Bird-dog primarily. We looked at their Zazz-OVL and even during today’s SVA training locally (http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf) we were discussing how complex some of the OVL choices could be and I mentioned ZazzOVL – as the Dutch puts it, it is “jammer” (pronounce it as “yammer”, see: http://forum.wordreference.com/showthread.php?t=359560) that we didn’t have the tool handy to show off the value (during the lab session I mean). So make no mistake – their ZazzOVL is very very handy indeed – if you are adding OVLs that’s.

Coming back to their offerings – Bird-dog is a very interesting approach, very much for those assertion enthusiasts who look for “where is the maximum ROI of adding assertions”. Their Visual-SVA is like a “temporal GUI/editor” for complex SVA coding, not my personal cup-of-tea, but I do see value for some there. However generating “traces” for assertions within Visual-SVA is certainly a good attempt. Let’s see how they fair in real life usage! Visit Zocalo Tech Booth # 1509

The all new UVM (a la erstwhile OVM)

Sure you have heard of that – UVM, a sincere effort from Accellera to arrive at a “Universal” methodology from those seemingly competing OVM & VMM. Unless you want to risk your company not paying off your DAC bills, you wouldn’t want to miss that UVM booth :-) Honestly – I believe every one is looking forward to that. As the Accellera PR puts it:

Accellera's DAC breakfast, sponsored by Cadence, Mentor and Synopsys, will feature a standards update with an overview of how the Universal Verification Methodology (UVM) standard supports verification tool interoperability and gives IP and EDA users more choices, and a panel on "UVM: Charting the New Territory." This event continues the celebration of Accellera's 10 years of standards excellence.

For the first time, all 3 major vendors “sponsor” one event promoting ONE methodology – a great news indeed for the users. BTW, there is Aldec catching up on the SystemVerilog support with Riviera-Pro product line. Ask them for VMM/OVM/UVM support updates at: http://www.aldec.com/registration/dac

Agnisys's OVM/UVM management kits

A young EDA company based in Noida, India with solid EDA background (Anupam). They have iDesignSpec & iVerifySpec as products - one is for Register automation and another for overall Verification management. The REG automation has been a long awaited/wished for stuff, almost 8 years back we at Intel used Perl+DOC (Table) for something similar - glad to see a much more finished end product now. It can emit VMM-RAL, OVM and soon perhaps the UVM code too.

Sapient-Inc's IC management

Another young EDA company, according to the founder - Subash, a long time chip designer/manager:

I started Sapient-IC from the pain and frustration of managing IC products. The die size grows, schedule slips, VP yells at everybody. This is what I want address. Analytics for decision makers, comparative analysis for design choices to financial analysis.

Breker’s Trek

A not-so-young EDA company (compared to the likes of NextOp/Zocalo etc.) with some interesting success stories with NVidia, STMicro. Their Trek is certainly a refreshing approach to testcase writing – especially for SoC Verification. See: http://www.cvcblr.com/blog/?p=148 for more details.

RealIntent’s Ascent

So much has been told, written about Linters – yet its adoption has been hampered heavily by the amount of “noise” it creates. Realintent’s Ascent claims to be less on that – and that is their primary seeling point. Not sure how they achieve that – given the natural side-effect of trying “find faults” with any given code.

SpringSoft

Check with them what’s up with their Certess/Certitude – it is an innovative approach for sure – mutation based TB qualification. As much as we have heard locally, there have been success and also some additional “noise”.

NextOp's assertion synthesis and our recent FIFO experience

2010-05-24T19:27:00.000-07:00

Based on DVCon 2010 paper on SystemVerilog Assertions - 2009 (see www.cvcblr.com --> Publications) we recently got our FIFO model run through NextOp's BugScope tool. It produced some interesting stuff. The main one I liked is

pop |-> full;

This is an eye opener property - as this should never be the case! But BugScope indeed indicated that we are missing this - either as assert or cover. Obviously this is not a good assert, so when we analyzed deep, it turned out to be a "valid coverage" based on the RTL written. Details at:

http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=18073#18073

So essentially we did have a coverage hole - when that hole is analyzed, we get a design error/bug! What an interesting go-around way of detecting bugs - who cares, as long the bug detection is automatic, it is good!

Ajeetha,

http://www.cvcblr.com/blog/?p=163

Welcome the next generation Verification Methodology – UVM

2010-05-17T09:21:00.001-07:00

For all those System Verilog geeks, lovers, followers here is a sigh of BIG relief – at last we have a UNIVERSAL Verification Methodology that all the 3 major EDA vendors would openly support (and hopefully promote as well). As we speak, UVM-EA (Early Adaptor) release is now available. Take a look at it from Accellera site.

CVC (www.cvcblr.com) has been constantly following this release and are about to release our fresh trainings on this UVM. After all it is based on OVM 2.0.* on which we had successful trainings delivered to several customers locally. The most recent one just over the last weekend! (Yeah, we do have weekend classes as well).

So, what are you waiting for? Go ahead and ask for our upcoming UVM class via training@cvcblr.com or call us via +91-9620209226

Talk to you soon on UVM!

CVC Team

www.cvcblr.com

A glimpse of our DVAudit – what goes on @CVC’s TDG

2010-04-24T02:11:00.001-07:00

Many have asked us the following:

Is CVC a training company? I see: www.cvcblr.com/trainings
Do you work on “live” projects?
What is your TDG really doing?

and more. Usually these questions are more from students/RCGs (Recent College Graduates) than the experienced lot – as the experienced lot is well networked with CVC founders (www.linkedin.com/in/svenka3, www.linkedin.com/in/ajeetha) and can hence know about us well.

Our honest answer to such questions is “all of the above” :-) That’s YES, we ARE proud to be a training company www.cvcblr.com/trainings – simply b’cos we know why we are doing that. We work on “live” projects – we constantly upgrade to next generation technology, the most recent being the SystemVerilog VMM/OVM, Low power etc.

What makes us really different and keeps us constantly innovating is the thirst for “doing better”. This is the core of our PDG – Product Division Group (yet to be formally announced on our website), we look for ways to enhance the productivity. For instance when there is a customer deliverable for a Verification code, “Team CVC” spends quality time together to do thorough reviews, code walk through, custom lints etc. Here is our latest, weekend edition on un-moderated, live-from-the board glimpse of our DVAudit review done on a customer deliverable.

For the experienced lot reading this entry (BTW, thanks for getting so far :-)), this is such a common part of your tech-life. For those uninitiated, this is how industry works - “writing piece of code” is just A part – there is lot more to it in making it customer ready/production ready.

Now what’s innovative about the above “glimpse” – if you read it carefully you can observe that we are creating a thorough check-list of “executable” process for Design-Verification Audit. It is something CVC has been doing it for its corporate customers behind the scene for many years. Now it is slowly taking shape as part of our PDG – stay tuned for more..

A modern approach to SoC level verification

2010-03-17T11:22:00.001-07:00

Verifying SoC is fun and tedious. Especially with several buzz words around the corner, it is quite easy to get lost in maze of buzz-words and miss the goal. At the end one may feel that the plain old wisdom of whiteboard based testcase review/plan is/was lot more controllable & observable. We did that back in 2000 @ Realchip communications and yes it worked really well. But with shrinking times and mounting complexity is that really fast enough? Before I hear constrained-random, blink for a while – how much random do you want your end-to-end data flow in-and-out of ASIC/SoC to be?

We at CVC (www.cvcblr.com) take pride in partnering with all major EDA vendors (http://www.cvcblr.com/partners) – big & small to look for best possible solution for different problems than suggesting “one-size-fit-all” like solution.

Here is a relevant thread @Vguild: http://www.verificationguild.com/modules.php?name=Forums&file=viewtopic&p=17615#17615

I am due to start work on an ASIC, and am wondering about a suitable verification strategy. The ASIC consists of a data path, with continuous data input from ADCs and continuous output to DACs, and a couple of embedded processors utilising external flash and SRAM.

So the interfaces to the ASIC are pretty much:
(1) parallel data bus in
(2) parallel data bus out
(3) external memory interface for CPUs

And here is our own experience/view of some emerging approach to this problem – we don’t claim to have solved it completely, but seem to be making good progress towards a methodical and controllable (yet scalable) manner.

Hi Siskin,
Good question/topic. While the value of OVM/VMM is very profound at block levels, their usage at SoC level wherein end-to-end data flow is being checked is not very well reported (yet) in literature. Needless to say they are far better than inventing your own. Especially if you have block-to-system reuse of these VIP components they definitely come very handy. The virtual sequences/multi-stream scenarios do assist but IMHO they come with heavy workouts. Instead what we promote to our customers here and have been proto-typing with at CVC is the solution from Breker, it is called Trek. It can work on top of any existing TB - Verilog/VHDL/TCL/VMM/OVM you name it.
Idea is to reuse the block level components to do what they do best and build tests at a higher level - in this case using graphs, nodes etc. I tend to like this as I used to like Petri nets during my post-graduation days (though didn't followup on my interest afterwards).
My first impression was to use Trek simply as a testcase creation engine but slowly I'm getting convinced it is useful as "checker" as well - especially the end-to-end checks.
You are absolutely right - use assertions in IP interface levels and use some sort of higher level stimulus. Where I see Trek useful in SoC verification is the ability to describe your "flow of data through SoC" as a graph and let the tool generate tests for you. I even jokingly say one can use a palmtop/PDA to draw these graphs during travel, convert them to Trek graph (somehow, didn't chase that dream yet) and have tests ready while I'm on travel - flight/train/bus whatever be it! On a serious note, this is quite similar to how we used to discuss our testplans on a whiteboard during our Realchip (a communication startup in 2000-2001) days, now becoming "executable"
See ST's usage of Trek @
http://www10.edacafe.com/nbc/articles/view_article.php?articleid=787856
Feel free to contact me offline if you need further assistance on Trek. We have our 2nd successful project finishing on using Trek, though these are small/medium scale ones.
My 2 cents!
Srini
www.cvcblr.com
_________________
Srinivasan Venkataramanan
Chief Technology Officer, CVC www.cvcblr.com
A Pragmatic Approach to VMM Adoption
SystemVerilog Assertions Handbook
Using PSL/SUGAR 2nd Edition.
Contributor: The functional verification of electronic systems

NextOp’s Assertion Synthesis – expanding ABV applications?

2010-03-13T11:06:00.001-08:00

In case you missed it, read a user report on NextOp’s technology at: http://www.deepchip.com/items/0484-01.html

In next couple of blog entries, I will share my reading, reflections on this detailed report.

To start with, this technology seems to address some of the “points to ponder” being discussed at: http://www.cvcblr.com/blog/?p=146

As there is no whitepaper/material available on this technology I base my reflections solely on the ESNUG report. First thing that strikes me is, it seems to suggest in identifying “what assertions to write”. But then it takes a radically different approach to this problem atleast from what has been attempted so far by other EDA vendors. The single most difference is it takes the RTL + Testbench as guide to create assertions/properties. From the report:

 BugScope
takes in our RTL design and testbench as inputs and generates properties,
(which we then categorize as assertions or coverages) that help identify
bugs and coverage holes during simulation.  In contrast, Mentor's 0-in
assertion synthesis does not use our testbench;

This is certainly new idea, though I’m little sceptical about the value of late-in-the-cycle assertions.

The next interetsing inference I have on this report is the “coverage property” generation:

When we began our BugScope eval, we only cared about assertion properties
it generated -- we didn't initially see any value of BugScope's coverage
properties.

From what I read in that report, its USP seems to be the “coverage holes” that it can identify. In which case it may be adding more work for the whole project than reducing it – true it helps with better quality, but folks like nuSym will go crazy to have more to cover, but again it is too early to comment in detail. The example given in that report looks little strange as that case maybe due to insufficient run-time of testcase, weak random generation, over-constrained stimulus etc. Also nowadays with RAL (VMM-RAL, www.vmmcentral.org) like automation, all registers can be captured in more controlled fashion from spec. So atleast I fail to see value with the example provided in the report. But since the user says he is using it in production for 2 years or so, there must be credit to this “niche technology”.

Perhaps NextOp is expanding the traditional ABV applications to include “verification closure requirements” by identifying what is not covered yet. That will be interesting application of ABV!

ABV – points to ponder on its slow adoption

2010-03-13T10:49:00.001-08:00

Efforts have been ongoing to make ABV (Assertion Based Verification) more and more deployed for several years via OVL, PSL, SVA etc. Though the concept of assertions is not really new to the industry, widespread usage of it has not been as much as it was expected atleast by the EDA vendors, promoters (to which I consider CVC www.cvcblr,com included).

Prior to PSL/SVA days, 0-in came up with idea of assertion identification, checker library etc. It did catch up with early adaptors but suffered from proprietary solution and inherent limitations of any auto-generated code. This was followed by other EDA vendors developing “auto-generated assertions” for designs – there was some good traction for few quarters and then the initial enthusiasm faded away as the SNR (Signal-to-Noise-Ration) was way too much perhaps.

The development of OVL and other vendor specific assertion libraries looked promising, but IMHO this was not marketed well enough. Also they all fell short of good old 0-in checker elements when it comes to ease of use, verbosity etc. We dealt on this very topic in good detail in our rceent SVA handbook 2nd edition (www.systemverilog.us/sva_info.html) and also touched upon this in our DVCOn 2010 paper (See www.cvcblr.com for downloads page, code, paper + slides are available on request).

As we at CVC have been walking through these developments in the industry we continue to have debate on what is preventing it from being more widely used. We have several items identified, a non-exhaustive list is below:

Who will add these tiny little monsters to start with? Is it RTL designers or Verification engineers?
- The answer seems to be both.
There is a myth that RTL folks don’t want to learn new language – be it SVA/PSL etc.
- I call it a myth b’cos atleast in this part of the world, the young engineers are always open to new languages, technologies to keep them ahead in technology and beat recession!
- True, the full PSL/SVA is more than what average RTL guy can consume – but then the kind of properties that RTL folks would write are also simple and don’t require full language capabilities.
- We at CVC have carefully extracted what RTL designers would require to become productive with ABV – we offer it as 1-day (or even half-a-day if really needed) workshop on “ABV for RTL designers”, see: www.cvcblr.com/trainings or contact us via training@cvcblr.com for details
The checker libraries are very handy for RTL folks, but as I said earlier many are not even aware of its potentials. Need more marketing..
- Some complain about the verbosity especially those who have used 0-in or OVA (inlined) in the past (See AMD’s presentation to Accellera OVL-TC www.accellera.org few years back)
  - Recently released SVA-2009 LRM does address this well with inherited clocks, default clock etc. See www.systemverilog.us for more
  - Also look at checker..endchecker construct in SVA-2009
- Many users may indeed benefit from a simple “drag-n-drop” style such as the one being developed by ZazzOVL (www.zocalo-tech.com) We at CVC have done initial eval and results look very promising. True, they have some way to go before satisfying every possible user, but good first step I must say!
In My design, what assertions can I add?
- This seems to be much more prevelant question than the myth I mention earlier. There is good element of truth in this concern – only with experience does one get to “identify” quality assertions.
- There are tools emerging in this space such as NextOp’s Assertion synthesis @:http://www.deepchip.com/items/0484-01.html and Zocalo’s “Zazz bird dog” (www.zocalo-tech.com)
How do I know whether my assertions themselves are correct?
- See: http://www.cvcblr.com/blog/?p=132 for a lively discussion on this topic with Jasper’s ActiveDesign seemingly addressing this well along with other EDA vendors too.
- Also tools like VCS, Verdi etc. allow assertion evaluation based on a given DUMP file – say VPD, FSDB etc. This is yet another useful feature that’s least marketed – if any. Do look in the tool doc or contact your vendor for more on this, or send us an email via: info@cvcblr.com for more on this.
How do I know my assertions really fired?
- Good question, look at assertion coverage and more interestingly the methodology note recently added by our team @ VMMCentral (www.vmmcentral.org) on the concept of “totally vacuous” assertions. See: http://www.cvcblr.com/blog/?p=143 for more.
How many assertions are enough for my design?
- Excellent/Best question perhaps, so NO ANSWER :-)
- More pragmatically though, there is some research going on at IIT-Kharagpur on this topic, see: http://www.smdp.iitkgp.ernet.in/publications.htm
- 0-in addressed this with MSD – Minimum Sequential Distance, look in their doc for more
- VCS adds a stats on “assertion density” – some indications atleast
- If you are a Masters graduate or PhD – excellent topic to work on!

Twitter of RTL design – welcome to Behavioral Indexing!

2010-03-13T09:07:00.001-08:00

Srinivasan Venkataramanan, CVC Pvt. Ltd. www.cvcblr.com

Ajeetha Kumari, CVC Pvt. Ltd. www.cvcblr.com

If you haven’t heard of Twitter you perhaps are living in an internet vacuum J On a positive note, the reach and impact of SNS (Social Networking Sites) into our internet life is hard to ignore – whether it is Twitter, Facebook, LinkedIn etc. To me, a successful SNS tries to capture “what is in going on in your mind right now”? A similar approach can be applied to RTL design – when a designer makes an assumption about the latency of output or the FIFO size etc., it hardly gets captured in a repeatable, executable format. True, at the end of a design phase documentation is written (usually) that attempts to capture these. However it gets too late by then to be “active comments”.

From a language perspective SystemVerilog allows assertions & functional coverage (covergroup) inline with RTL code that can help to some extent. However they are only the “specification” part. A lot more “information” gets lost during such translation such as

· “show me a proof/witness/waveform” for such an occurrence

· Can we optimize the latency to say 5

· What-if I change the FIFO size to 32 here etc.

Jasper’s recently announced ActiveDesign technology has a significant component for this “design process”. It is called “Behavioral Indexing”, you “index” the behavior with facts, assumptions, traces, bugs etc. all in a comprehensive database along with your RTL. So when a designer (or another designer who inherits, reviews the code) looks at the code again (via the ActiveDesign database of-course) he/she can get not only the assumptions (that would be similar to SVA) but also real traces, potential issues of changes to FIFO size etc. In a generic sense the indexing captures the designers state of mind “at that point in time” as a snapshot and keeps it reproducible throughout the lifetime of the RTL code! A good thinking indeed, this is why I like to call it the “Twitter of RTL design”.

There is more to Behavioral Indexing than this, will talk about it next time around, so stay tuned!

Introducing “totally vacuous” assertion attempts

2010-03-10T08:29:00.001-08:00

See our interesting Blog post at: http://www.vmmcentral.org/vmartialarts/?p=1130

On the topic of adding SystemVerilog “bind files” – a new tool that is shaping up can help automate even that part – see ZazzOVL (www.zocalo-tech.com). Though as of now it works only for OVL, technically speaking it is very easy to extend it for user specified assertion libraries/modules/MIPs etc.

Identifying transactions faster with Verdi

2010-03-07T08:16:00.001-08:00

Further to our previous blog entry on Verdi’s advanced Transaction debug features (ref: http://www.cvcblr.com/blog/?p=130 ), here are some more tricks that can help debug automation even further.

Very often designers find that there are certain unique characteristics/attributes that differentiate transactions. For instance Transaction kind being ERROR/SPLIT/RETRY etc. Wouldn’t it be nice if on a 50,000 clock cycle simulation dump one can:

Quickly identify the “information” from “raw data” of signal toggles? (see: http://www.cvcblr.com/blog/?p=130)
On top of previous item, classify the transactions based on user specified “attributes/fields” such as ERROR/SPLIT/RETRY

This is very handy trick with Verdi. Select Message –> Filter/Colorify as in screenshot below:

Once you are there, define the attributes in the dialog/pane as shown below:

Voila! You get:

Add with the signals involved:

Now, that’s true “debug automation” and “raising debug abstraction level” in pragmatic sense!

Smart application of vmm_log::disable_types()

2010-03-02T08:46:00.001-08:00

Srinivasan Venkataramanan, CVC Pvt. Ltd.

Ever wonder why typical SystemVerilog base classes are bulky and seem to make life complicated against simple things like $display? The devil lies in detail – true simple $display is the easiest to use, but think about the code you are writing to have longer life and reuse – then you slowly start realizing the need. Sometimes you need to get bitten by the downside of not using amethodology to start appreciating the need for methodology.

See: http://www.vmmcentral.org/vmartialarts/?p=1098 for a smart usage of vmm_log::disable_types() method. Many folks have asked me why the VMM_LOG is so bloated (in their view), the above is just a sample, see more @ http://www.vmmcentral.org/vmartialarts/?p=259

Look ma “No RTL, TB, only PSL/SVA – yet I can validate my spec”

2010-03-01T08:20:00.001-08:00

It is one of those most commonly asked questions in any assertions training/engagement – assertions describe design behavior, but how can I validate my assertions even before my RTL and/or TB is ready? This is useful for few reasons:

1. Users new to writing assertions using PSL/SVA are expected to make mistakes in assertions initially. So it will be good to get some quick waveforms and validate the assertions in stand alone fashion.

2. While the spec is vague, it creates a mechanism to develop/solidify the spec itself

Typically during the advanced sequences/SEREs section of our PSL (http://www.cvcblr.com/trng_profiles/CVC_LG_PSL_profile.pdf) trainings or SystemVerilog Assertions trainings (http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf) this question invariably comes up.

In principle this is a sweet spot for formal tools (Model checkers) – though not all of them openly promote this nice “hidden gem”. I had first hand experience of doing it via some scripts inside Synopsys not too long ago. But not every user is made aware of this “non-productized” feature.

Here is what Jasper had to say on this:

The idea you have mentioned about visualizing assertions in SVA/PSL without DUT/TB has been around within Jasper, for a long while. At that time, one of our customers is trying to train more people within their company to write PSL, and many of the engineers found it easy to write "incorrect PSL", and would like us to provide a tool to help them understand whether the PSL they have written captures the intended behaviors.

I also heard atleast one another EDA vendor confirming its tool being able to easily do this. I will add that name if I get clearance :-)

So as my co-author Ben Cohen (www.systemverilog.us) always insists – YES one can (and perhaps should, for a class of designs/specs) use assertions in SystemVerilog (SVA) and/or PSL during the micro-architecture specification stage itself.

Welcome to the new world of possibilities – true this capability has been around for few years, but I haven’t seen many fully exploiting it yet.

Transaction Level Debug with SystemVerilog/VMM and Verdi

2010-02-26T09:24:00.001-08:00

In our regular SystemVerilog, VMM trainings (www.cvcblr.com/trainings) we demonstrate the power of callbacks to go beyond the obvious usage – specifically a case study to demonstrate transaction level debug. While this topic has been around for very long time (IIRC, Cadence/DAI first provided it via SignalScan), its real application in day-to-day debug has not been as popular as it should probably be.

Some reasons for the slow progress in debug are due to the tool limitations, some due to user unawareness etc. Today we had this session again at CVC and users really liked it a lot. We decided to open up this stuff as there is more interest and share it with larger community.

We also got Verdi (tm) working on this design with simple addition of $fsdbLog – one doesn’t require extra virtual-interface anymore! Hurray! The Debug champion has once again provided a very useful feature for SystemVerilog, class based environments to be debugged effectively. See some of the screenshots below. A much more lively demo can be seen at:

http://www.slideshare.net/svenka3/transaction-level-debug-with-systemverilog-vmm-verdi

Add simple code for $fsdbLog – similar syntax as $display:

Start seeing transactions in Waveform (FSDB)

Verdi also presents a transaction browser in TEXTUAL form as shown below:

But to be honest – one needs to see the demo with action, try:

http://www.slideshare.net/svenka3/transaction-level-debug-with-systemverilog-vmm-verdi

for a PPS style. I’m also uploading a Video capture soon. Hopefully it goes through, then it will be lot more fun. If you wish to see it live on your designs, call us via info@cvcblr.com or www.cvcblr.com

Potential research areas on ABV – for a Masters thesis

2010-02-25T09:09:00.001-08:00

As part of our BUDS internship program (http://www.cvcblr.com/downloads/BUDs_CVC_Acad.pdf) we work with some of the leading edge educational institutions in India (and one in the USA, BTW). One of our current inters is working on Assertions Based Verification using OVL. In less than a month he has picked up so much so that he says he has learnt more than what he had done (practically) in last semester – it is about that self satisfaction that we consider as our success.

During a recent review at his college, his guide, a very respectable professor in this domain (He is the DEAN of M.Tech VLSI there) has given a very constructive criticism saying:

OVL is fine, but can you add some research work beyond what is obvious/common use to your thesis?

We at CVC felt very happy about that comment – as it reflects on the reviewer’s thirst for highest standards and research inclination and keep us more motivated to go beyond the obvious. So we than him greatly for his inputs via this blog.

Today during a review session we agreed on some of the research topics in this domain, feel free to add anymore if you come across. Even if the present intern can’t take all, a future one can build on this work!

Assertion Density –> How many assertions are enough for my design? Look for some research work @ IIT-KGP (http://www.smdp.iitkgp.ernet.in/publications.htm). Also tools like 0-in, VCS etc. present some code level metrics to assist in this space. But more needs to be done. Say assign a “weight” to each OVL element, classify them as per their complexity etc.
Clock Domain Crossing (CDC) Verification using Assertions
Low Power Verification using Assertions
Assertion candidate identification on a given RTL – such as the emerging Zazz bird dog (tm) (http://zocalo-tech.com/products.php)
Assertion Visualization without any TB/RTL. A seemingly close to it technology is available from Jasper (www.jasper-da.com) via their recently announced ActiveDesign (tm) product.

I encourage others to add more topics as comments to this entry so that the academia can focus on next generation challenges!

Why CVC’s trainings are so special

2010-02-25T08:49:00.001-08:00

As in any business, there are always lead players and those who try to “mimic” them. We see our trainings also the same way – let’s admit there are few players in this game in our region. However what sets us apart from the rest? Few:

1. First of all we serve the whole industry at large:

Be it a fresh graduate (via our EIC: http://www.cvcblr.com/trng_profiles/CVC_EIC_profile.pdf, http://www.slideshare.net/svenka3/anubhuti-engineering-incubation-centre-eic)
An experienced, mid-career engineer looking to re-skill, recently SystemVerilog being the runaway success (http://www.cvcblr.com/trng_profiles/CVC_VSV_WK_profile.pdf)
Engineering managers, marketing execs who want 10,000 foot view of the VLSI ball game
Sometimes, engineers from other domains (SW, Mechanical – yes we had one!!) willing to learn basics of Verilog.

Such a wide coverage of audience is very rare if any, even across globe. Again note that many may promise, it is important to deliver and that too with passion and from real experts, who can be named, identified than those typical “interact with industry experts” kind of statements!

As one of our testimonials (http://www.cvcblr.com/testimonials) go:

"...have been practicing for many years just what they teach now. A giant step in the right direction to introduce a quality VLSI design and verification in India!"

Sunil Kakkar, Chief Architect - SKAK INC.

2. We believe in what we do – yes we do NOT cover the whole VLSI flow – every wonder why? Espeically given that other training institutes here do claim that as a BIG deal? Recently an Aldec engineer (Purushottham) here said this:

I wonder why anyone would want to “specialize” on the whole VLSI flow, a typical ASIC/VLSI engineer works for several years on a specific role – either front-end or back-end, and not on both.

At CVC, our belief is that we should create employable talent pool than just some diploma, certificate holders. We infact receive several such resumes for our TDG division from other institutes, recently we had one – someone who is teaching Verilog at an institute, when asked to write some code and add “comments” used “ \\ Verilog comment “. Nothing against any specific individual or org, but just to reflect the state of what we saw.

Indeed I’m grateful to such experiences – that made us to realize the need for our EIC – an incubation center than just a training institute.

It is our genuine interest to place all our trainees – be it freshers or experienced ones – either through our industry contacts/existing customers or internally for our consulting projects. But we have very high levels of quality requirements to be placed – right from code indentation, linting, synthesis to verification. Unless the design, coding, tool usage everything measures upto our quality standards we just can’t hire folks into our TDG – we make that explicit every time we get a chance and NOT at the end alone!

So – to summarize, we BELIEVE in what we do, so if you are looking for a successful career and are willing to put in sincere efforts on your own, come and contact us training@cvcblr.com

Thanks for reading!

www.cvcblr.com/blog

Debug SystemVerilog code the right way with Verdi

2010-02-24T09:35:00.001-08:00

Srinivasan Venkataramanan, CVC Pvt. Ltd. www.cvcblr.com

Sreenath V, CVC Pvt. Ltd. www.cvcblr.com

One of the many challenges in taking over a block developed by others is the quick ability to grasp the big picture fast and then delve deep into some focus areas. Talking of SystemVerilog based Verification code base (say with a base class such as VMM) is even more challenging as many engineers still find it new. During recent reviews at customer sites we often find engineers asking questions like:

1. How do I quickly know the various transactors in my environment? Of-course one can go through UNIX find-grep route, but with modern verification base, there has to be a modern approach to this ever lasting challenge as well.

2. With several macros being used to reduce the verbosity in coding, the reading/deciphering the code by a novice engineers becomes more challenging. If tools don’t address this part, it is possible that the benefits of code shrink by these macros may get quickly lost with the time being spent by a new engineer trying to understand it in detail.

SpringSoft’s Verdi (tm) has solid support for SystemVerilog testbenches with a full fledged Testbench browser, macro expander etc. It also provides a nice transaction debug capabilities, more on that on a separate blog soon.

What is nice about Verdi is the ability to get a quick view of inheritance structure via its Testbench Browser. See below for an example (look at the Green eclipse area). It is very easy to note the transactors derived from a base class such as vmm_xactor.

On the second challenge, Verdi makes it very convenient to expand/collapse a macro.

1. Select the macro usage on the source window.

2. Press “Control-m” – expand macro; See below for a screenshot, l

3. The source window now has an expand/collapse icon (+/- symbol) to the left of the macro line. (Green eclipse below)

4. When you expand, the “behind the scene” code gets colored on w white background quickly making it distinguished from rest of the code. ((Green rectangle below).

We recently had a customer asking for all VMM component code expanded, and it was merely a 15 minute job with this tiny little feature to get that done!

Happy debugging!

Early validation of RTL – with no Testbench!

2010-02-22T23:07:00.001-08:00

Srinivasan Venkataramanan, CVC Pvt. Ltd.

Looks like Jasper DA (www.jasper-da.com) is on a mission to drive simulation a passé J On a more serious note, their recently announced ActiveDesign (TM) technology sounds pretty interesting for early RTL validation. Before I hear that “Aha..that’s my favourite LINTing”, hold on.. this is much more than that – one can see real waveforms– no testbench is ready yet, but the tool can create quality waveforms for you!

Sounds too good to be true, well their demo indeed shows a very representative real life design – AHB-lite to AXI bridge with 4 AHB-lite masters.

I had a chat with the ActiveDesign team recently to understand what goes “behind-the-scene” (Norris Ip, Holly Stump & Saptarshi all from Jasper). My main doubt on this “early RTL validation” was whether it can work for custom protocols and whether user needs to provide some assertions to get this working. These questions are relevant because we at CVC have prototyped similar stuff for standard protocols via our SVA/PSL based MIPs (Monitor IPs) and some commercially available tool features from other EDA vendors – it involves few hacks and scripting, but doable – if put in some hard work. It requires either an advanced SVA/PSL aware simulator or a model checker/formal tool.

Coming back to Jasper, the short & sweet answer is:

“No, user doesn’t have to create any assertions for getting this. The tool analyzes the RTL code and , based on a few user-interactions with the GUI, waveforms are created". And yes it does work for any design not just for standard protocols” As a side note the tool can create SVA code for the “behaviors/recipes” – more on it later.

The technology is built around Jasper’s popular and proven Visualize (TM) and recently announced “Behavioral Indexing (TM)”. More on the “behavioral indexing” in one of my next entries.

For now, if you are developing a fresh RTL and want to validate it without having to wait for RTL to finish, TB to be ready etc. look at ActiveDesign. Of-course I also highly recommend running LINT before you do that, though Jasper doesn’t have that in this platform. You may want to try some of the new linters such as Aldec’s ALINT, see: http://www.cvcblr.com/blog/?p=99 for a fresh look at Linters.

Signs of maturity in EDA tool built-in examples

2010-02-21T02:21:00.001-08:00

During a recent look at ActiveDesign product from Jasper (http://www.jasper-da.com/products/ActiveDesign.htm), I was pleasantly surprised to see a high quality design being used as the case study. Usually such early product demos contain tightly canned examples, showing only the relevant tool features and much less on the actual design. Here is a refresher – we get a very representative real life design – AHB-lite to AXI bridge with 4 AHB-lite masters, a refreshing change in EDA space.

See below for a screenshot of the demo design:

Tool demos are not on dummy designs, becoming more and more realistic indeed!

On a similar note, Breker’s Trek (www.brekersystems.com) has $TREK_HOME/examples that are complete SoC level test synthesis – not just “Hello World”, “foo-bar” anymore! Other interesting designs include a Cache controller model, CPU etc.

Similar is the SoC kit initiative from Cadence (www.cadence.com/products/fv/iv_kit) – this one tops the list of all EDA demos I’ve seen in years on Verification – they started back in late 2007 and have been growing in strength over years. During CDNLive 09 @ Bangalore, CDN showed their roadmap for these kits and clear indications are that these will be extended to ESL platforms too.

Sure all vendors ship more and more examples with their tools nowadays, this also means they employ/engage with real verification engineers besides R&D, support engineers, good for the job market, hopefully :-)

SystemVerilog covergroup – bins and the value set matching

2010-02-13T09:46:00.001-08:00

During our last week Verification with SystemVerilog class (VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ), an interesting question popped up during functional coverage session. As user defined bins are created for vectors in SystemVerilog, what if the value set range is not divisible by the specified number of bins (say in a fixed number of bins case)?

Consider:

[cpp]

bit [4:0] vec_5bits;

covergroup cg;

cp1 : coverpoint vec_5bits {

bins four_buckets [4] = {[0:$]};

bins five_buckets [5] = {[0:$]};

bins fifty_buckets [50] = {[0:$]};

}

endgroup : cg

[/cpp]

Let’s analyze the above:

four_buckets –> simple, each contains 8 values, uniform

five_buckets –> 5 buckets, first 4 will have 6 values each, 5th bucket will contain all the remaining 8 values:

[0,1,2,3,4,5], [6,7,8,9,10,11], [12..17], [18..23], [24,25,26,27,28,29,30,31]

fifty_bukcets –> first 32 bins will have 1 value each, remaining 18 shall remain empty!!

Questa prints a nice warning about the last case as below:

VSIM 1> run 990
# ** Warning: (vsim-8546) The number of values specified '32' is less than the size '50' of fixed-size array bin 'fifty_buckets' in Coverpoint 'cp_1' of Covergroup instance '\/top/spram_fcov_1/my_cg_0 '. The '18' empty bins will not contribute towards coverage.

Debug SystemVerilog macros with VCS-DVE

2010-02-07T16:33:00.001-08:00

Srinivasan Venkataramanan, CVC Pvt. Ltd.

Rashmi Talanki, Sasken

John Paul Hirudayasamy, Synopsys

An extract from a little lengthier post @ http://www.vmmcentral.org/vmartialarts/?p=922 – focus here only on Debug side on this post:

One of the powerful features of SystemVerilog is the ability to create TEXT macros (those `define s) with arguments – they can create fairly complex code in jiffy. Take a look at VMM source code if you need examples.

In a recent customer engagement, we had to dig deep into VMM atomic Generator code that gets created by the one liner macros!

During the coding work, the customer opened up vmm.sv and got trapped in the multitude of `define vmm_atomic_gen_* macros with all those nice looking “ \ “ at the end – thanks to SV’s style of creating macros with arguments. Though powerful, it is not the easiest one to read and decipher – again for a first time SV/VMM user.

Now comes the rescue in terms of well proven DVE – the VCS’s robust GUI front end. Its macro expansion feature that works as cleanly as it can get is at times hard to locate. But with our toolsmiths ready for assistance at CVC, it took hardly a few clicks to reveal the magic behind the `vmm_atomic_gen(icu_xfer). Here is a first look at the atomic gen code inside DVE.

Once the desired text macro is selected, DVE has a “CSM – Context Sensitive Menu” to expand the macro with arguments. It is “Show à Macro”, as seen below in the screenshot.

With a quick bang go on DVE – the Macros expander popped up revealing the nicely expanded, with all class name argument substituted source code for the actual atomic_generator that gets created by the one liner macro. Along with clearly visible were the facade class name and the actual callback task with clear argument list (something that’s not obvious by looking at standard vmm.sv).

Now, what’s more – in DVE, you can bind such “nice feature” to a convenient hot-key if you like (say if you intend to use this feature often). Here is the trick:

Add the following to your $HOME/.synopsys_dve_usersetup.tcl

gui_set_hotkey -menu "Scope->Show->Macro" -hot_key "F6"

Now when you select a macro and type “F6” – the macro expands, no rocket science, but a cool convenient feature indeed!

The DVE’s macro expansion feature that makes debugging a real fun!

Renewed interest/investment in code linting! Good for the industry

2010-01-20T08:13:00.001-08:00

As some of us have seen over last decade, approximately 5 years ago industry was upbeat about code/RTL linting with almost every EDA vendor offering products in this space. Some of them were start-ups acquired by big vendors (like LEDA.fr to Synopsys). At the end the Linting market proved too small for the 3 biggies and their focus on that technology got sidelined. In all, one company survived this wave well and that’s Atrenta – its SpyGlass product increased leaps and bounds both in its capabilities and installed base. Today SpyGlass is an undisputed leader in Linting and has enjoyed monopoly for more than 5 years, well done Atrenta!

Come recession, silently few smaller EDA vendors started investing on this niche segment and now we have ALINT from Aldec and Ascent from RealIntent. I’m personally thrilled to see more players on this technology – though the $$ may not be too high, the potential user base is large and investment is not all that HIGH as in a SystemVerilog simulator for instance.

From a user view though, Linting is a must have step in flow as recognized by experts like Adam Kronlik in a book: Functional Verification of Electronic Systems, Chapter 8 HDL Lint: http://www.iec.org/pubs/pub.asp?pid=13&bsi=3&cat=cont

(BTW, I have a chapter on the same book, Chapter 14).

Few notes on 2 modern linters here:

Ascent from RealIntent: (http://www.realintent.com/real-intent-products/ascent).

One of the traditional challenges of a Linter has been the “heavy noise” it creates. Recent Linters *claim* to do better there – especially Ascent.

Other interesting features in this linter are:

Opportunities to improve simulation performance
Operations with hidden or expensive implementation costs

True, your mileage may vary, but good thoughts indeed!

As we read more on the Datasheet of Ascent one gets a feeling that it combines a traditional Modelchecker inside it as well – as their PBV & ABV features talk about. I’m not sure if that’s a good thing from a pricing standpoint as the linters are usually far cheaper than model checkers. But a good try by RealIntent indeed!

ALINT from Aldec (www.aldec.com)

Fairly young in the market (~2 years??), it has solid STARC policy inside it. What really interests me in this is their full blown API for user defined checks – yes every other vendor claims/has it in some manner, but I have not seen this level of detailed support and even better – their flexibility and response time in enhancing the API as needed.

It will be interesting to see how they survive over say next 5 years! Maybe it signals some impact to the erstwhile King of Linting – SpyGlass!

SystemVerilog Interfaces – learn more about it for free! Register Now for this Webinar

2010-01-17T09:30:00.001-08:00

CVC is pleased to announce online Webinar on "SystemVerilog Interfaces" along with Aldec as our partner. With ever growing interest in the true power of SystemVerilog here is your opportunity to get started with SystemVerilog in good style with no additional cost - it is a FREE Webinar and is scheduled in 3 different times to suit various timezones across the globe - ASIA, Europe & USA.Register online NOW to book your seat!

ASIA - India 9.30-10.30 AM,China: 12.00 to 13.00

Europe - 15.00 to 16.00 CET

USA - 9.00 - 10.00 AM, PST

Click here for an abstract of the Webinar. It will be presented by Srinivasan Venkataramanan from CVC and Jaroslaw K, from Aldec.

Enabling Faster ABV – new initiatives

2009-12-22T10:23:00.001-08:00

Assertion Based Verification has certainly been one of the mostly debated topics over the last half-a-decade. So much so that one of the past DVCons was full of SystemVerilog & PSL papers on ABV that someone commented it is “ABV conference” than DVCon (was it DVCon 2005?2006?)

Even then the adoption rate has been slower than expected – agreed by many stats, EDA folks etc. A relatively new EDA vendor is addressing it via some tools, see: http://www.zocalo-tech.com/index.php

Not clear how easy it will be and how much ROI users will see, but an interesting development I must say.

With SystemVerilog 2009 LRM adding checker constructs we predict that the adoption of OVL-like libraries should dramatically improve. We explained it thoroughly in our SVA handbook 2nd edition, see: http://www.cvcblr.com/blog__resources

We have a DVCon 2010 paper on this very topic, see: http://dvcon.org/events/eventdetails.aspx?id=108-3

Let’s see how fast the checker gets implemented by EDA tools, we used VCS for our new book http://www.systemverilog.us/sva_info.html

Hope 2010 brings ABV more and more into RTL engineer’s desktops!

What is there in a number? No, it is not numerology – rather EDA marketing fun!

2009-12-22T09:50:00.001-08:00

For those of us who have been following the EDA marketing over several years, it is no surprise that there are dedicated marketing professionals within big EDA companies focussing on conveying message/confusing the ecosystem if needed (unfortunately). We have several anecdotes starting from “VHDL is dead” back in 2003 (http://www.eetimes.eu/uk/17408257) and guess what, last month we had a full-house “Advanced VHDL TB class” (http://www.cvcblr.com/blog/?p=86) and another one being scheduled in Jan 2010. I don’t intend to blame any single entity/individual for this, rather this is how it works, and those of us who have seen it for years understand it. Another classical case was for IEEE-1850 PSL – it is alive and kicking with becoming part of recent VHDL as well. Though not much development on PSL itself, but it is expected to stay for much longer than what some folks have predicted. Need a proof – name an EDA vendor without support for PSL – Mentor, Cadence, Synopsys, Aldec – all have them. It will be foolish to predict that all of these marketing teams went wrong with their predictions – if PSL were to be short-lived why have every EDA vendors invested in it?

Fast-forwarding to present day, recently SystemVerilog VMM 1.2 has been released (http://www.cvcblr.com/blog/?p=91) after a relatively longer incubation/Beta period than usual. And almost instantaneously we find Tom’s analysis at http://tinyurl.com/vmm12-20-ment – True VMM 1.2 has lots and lots of new stuff and even the old features have newer implementations (parameterized versions of channel etc. – maybe they were in VMM 1.1* as well?). But to the user community I believe this is a good thing – we are slowly seeing a sign of convergence to a CBCL becoming reality. Yes today VMM can run on 3 EDA tools and so is OVM. But how well do they interop? Ask Ashsih from Nokia Bangalore, he will tell you the horror stories he had since last 1 year or so.

Recently Accellera VIP-TSC established an inter-op kit, we saw that during recent SVUG here in Bangalore, see: www.svug.org for archives.

More recently (after the SVUG Bangalore event), the VIP-TSC has proposed a new name for this CBCL - “UVM” (No, not URM, rather UVM – fortunately this name has been spared so far by vendors). How this will shape up will be known in coming days, weeks, months if not years!

But it is clear that it will contain contributions from VMM & OVM and hopefully will run on all tools too. Having closely observed both OVM and VMM (1.2 including), there is easier migration path from OVM to VMM 1.2, if needed and vice versa, infact we present that as a handout to out regular training attendees who take up one methodology during training and pick up the other on the go!

With VMM 1.2 (Or 2.0, as per Tom) having similar concepts as OVM the creation of UVM should be lot simpler – we hope. Let’s see.

BTW, there is OVM 2.1 around the corner, should it be re-numbered? Anyone? Vaastu? Numerologists? Mentor is arranging a private Webinar for its valued partners for OVM 2.1 updates, so we should see another blog soon.

To me it is clear that the individual development efforts/bug fixes to both OVM & VMM will continue atleast till UVM 1.0 (??) emerges.By then will we see VMM 1.4? OVM 2.5? Anybody’s guess!

Enough on numbering! Let’s start the convergence, hope 2010 is a luck number for SystemVerilog enthusiasts as UVM should see its birth! Maybe Santa is granting UVM as a gift to SystemVerilog professionals :-)

SystemVerilog code automation from Puneet

2009-12-17T07:59:00.001-08:00

Good news for all those Emacs + SystemVerilog users. Puneet has just now released his SV Snippet for Emacs, see:

http://coverification.org/2009/12/17/systemverilog-snippets-for-emacs/

Will certainly try it out ASAP. Good start Puneet, keep it up. Thanks for sharing it!

Breakdown of Verification effort – Debug, Debug & more Debug..

2009-12-16T20:56:00.001-08:00

Interesting analysis of how Verification effort is being spent across industry:

http://tinyurl.com/dbg-it-man

(See the pie-chart, Figure 2). It goes very much inline with what we have been hearing from customers, competitors and also from our own own experience. So DEBUG is THE area if one were to automate within Functional Verification. I’m little surprised to see a 15% spent on ENV – perhaps it is the case for modern SystemVerilog/VMM/OVM stuff, but again that’s for the initial period I suppose. My belief is if you reuse VIPs, leverage on previous code and hire the right candidate, the ENV creation can be handled within 10% The testcase development is shown as 18%, not clear if some of it spread into the coverage bucket (another 15%) – as there is a strong correlation among the two anyway. I believe this is where technologies like Breker’s trek http://www.cvcblr.com/blog/?p=89 becomes interesting.

On the debug – the good old Novas/SpringSoft is still the leader with Siloti, Verdi and Debussy. Though I’m little disappointed at their SystemVerilog solutions – personally I would have liked more innovation on that space from these debug GURUs. They do have “log/transaction display”, but am sure more is in pipeline. A new company http://www.vennsa.com/product.html is showing up at places, will be interesting if anyone locally is using it. It will be worth getting some true success stories to see what exactly it automates.

Staying on the debug – I personally believe lot of these automation originate inhouse at customer sites. For instance during our Ethernet Switch/Router Verification monster, we created several scripts, plots etc. to do intelligent failure analysis (http://www.iec.org/pubs/print/verification_toc.html). Also our recent work with a local SAN customer resulted in visualizing AVL trees from running simulation. See: http://www.cvcblr.com/blog__resources and http://www.snug-universal.org/asia/india09_V1_Abstract.pdf

And then we had this SystemVerilog memory blow-up debug case, http://www.cvcblr.com/blog/?p=29 – so for now Debug continues to fascinate us the most!

Drop me a note if you would like to explore how you can automate your debug challenges.

Happy Debugging!

Formal Verification – Model Checking case study from SUN & Jasper – excellent read, to refer..

2009-12-15T10:51:00.001-08:00

In case you missed it: http://chipdesignmag.com/display.php?articleId=3723

I mentioned this during our recent Advanced VHDL TB class (http://www.cvcblr.com/blog/?p=86) during PSL session and attendees were very interested. Today I got a mail back from Chandramohan asking for the link, sent to him and read it once again (must admit, not in full indepth PCI-e level). Overall an excellent paper, perhaps a strong candidate for a DVCon Best paper award – real design bugs/scenarios listed..truly worth reading.

Such a nice paper didn’t have to have the following on simulation

Simulation, the alternative, brute force approach, ends up wasting resources and introduces additional risk. Even for cases where you think you understand the full state-space, it requires huge effort to develop a test strategy, e.g. complex test scenario with nested loops etc. Manual effort and test are required. Simulation cycles are long and regression test after modifications is slow. Furthermore, the designer generally has to edit down the simulation and remove certain combinations, without absolute knowledge of whether these are important or not. It is hit-or-miss because no design or verification engineer can enumerate all of these combinations.

With due respect to the authors – they seem to be cornering SIM way too side..One can forget the use of intelligent stimulus generation, adopting functional coverage, sequences, virtual sequences and even better the all new Trek (www.brekersystems.com) – their examples do contain similar PCIe stuff and it is quite powerful too. So let’s not write-off simulation, agreed – if and when formal works it is a great technology, but not at the cost of simulation..

VMM 1.2 is out…finally

2009-12-15T09:50:00.001-08:00

OpenSource VMM 1.2 is finally out, see vmmcentral.org – we have been mentioning it to many of our training attendees as “it is coming, it is coming”..now it is HERE!!

One of the greatest challenges we face is when our previous SystemVerilog/VMM attendees attend our newer classes (for upgrade, learn other methodology etc.) – they get very confused about the VMM channel (old way) vs. the new TLM way. The put/get definitions were simple, elegant, ready to use for first timers in VMM 1.0*. True the TLM adds lot of value, but existing users are finding it hard..This is where we folks like CVC fit in I suppose, so no complaints..

Enjoy and welcome the TLM way!

VMMing of a VHDL-C based Environment, anyone?

2009-12-13T06:27:00.001-08:00

Recently @VGuild Mike asked”

Does anyone use ModelSim's FLI for verification? What are the pros and cons of this?
I've been considering adopting SystemVerilog for writing test environments (we code our designs in VHDL and use PSL for assertions and functional coverage) but, from what I can gather, instead of SV I might as well just use ModelSim's FLI and write sophisticated testbenches in C. As an engineer, I am already very familiar with C, and so learning another language for verification (SV) is not desirable.
I suppose SV is more portable to other tools, rather than relying on ModelSim's FLI. And I suppose SV is supported by frameworks such as OVM. Other than that, why not use C/C++ as your verification language with the FLI?

Though the entire EDA marketing machinery is strongly biased on SystemVerilog, let’s realize that there is a sizeable population using VHDL, C etc. Few pointers for those unconvinced:

Our recent VHLD Advanced TB attendance here in Bangalore (http://www.cvcblr.com/blog/?p=86).
Continued interest from our customers on FPGA Verification courses: http://www.cvcblr.com/blog/?p=60
VHDL random generation, recent webinar @ aldec.com

So what’s the solution for VHDL users, looking at high-end Verification stuff? Is SystemVerilog THE only way? We at CVC believe SystemVerilog is “A way”, not necessarily THE ONLY way. For instance PSL becoming part of VHDL makes it a string candidate than SVA for VHDL users (yes even with recent SVA-09 features included http://www.systemverilog.us/sva_info.html, PSL’s LTL is long proven, well supported than SVA-09). I hear recently more momentum towards PSL from local VHDL users.

So coming back to Mike’s topic – few suggestions:

No single-size fit all solution
FLI is a choice if for foreseeable future Modelsim is bought over by your employer. But if there is any question of portability (given that there are strong contenders, pricing factor – did we not hear of BIG EDA vendor slashing prices like crazy – much like Magma style, but for verification?
I highly recommend to look at VHPI than FLI as it is IEEE standard and well supported by tools like VCSMX, IUS, Aldec (Riviera for sure, Active-HDL too I guess, anyone to confirm??)
For SystemVerilog like features – explore www.trusster.com for TEAL/TRUSS – akin to VMM/OVM without all bells and whistles, but provides a baseline and is FREE!! Can even run with Icarus for Verilog, hurray!!

So choose the right tool for the right job..

Breker’s Trek @DAC and CVC’s engagement so far..

2009-12-13T05:40:00.001-08:00

Another piece partly covered in Cooley’s report, but for those interested in full details (more technical updates coming in soon)..

Here are my (and my team, who is looking at it closely during an eval) observations on Breker's Trek tool. What we really like about this tool is that it an add-on to any existing methodology/environment (atleast we look at Verilog, SystemVerilog, VMM & OVM for now). Their marketing is also quite good in saying we solve the last 20% of the problem (which usually is the pain-point) though it needs to be proven (our eval is still in early stage). The BNF syntax looks interesting and for the uninitiated it may take a while, but certainly no big deal. We can appreciate the value such a tool brings in for testcase generation. However they claim to be eliminating the need for complex checkers - this is something we are still wary about and would like to delve deep into during the eval. In our view the checker part is hard and will be hard even with Trek. Our view of this feature of Trek is it is an ability to correlate the testcase and coverage to the checking mechanism - hopefully at a higher level of abstraction. If this can be achieved we would be glad with that. The coverage results annotation and reachability analysis part is really promising as it presents the test-coverage at a higher level of abstraction than traditional SV. In SV world one needs to code the complex covergroups, code/generate tests, correlate them and then view lower level coverage data (GUI/HTML/TEXT) to extract same kind of information.

Thanks

Shalini, CVC Pvt Ltd

Our NuSym updates from DAC and around..

2009-12-13T05:38:00.001-08:00

Some of you might have seen our report of DAC from John Cooley. Here is our full version of NuSym report for those interested. Trek to follow (wiht more updates after the DAC report was sent out)..

We at CVC have been tracking Nusym's technology for a while. I visited their booth & demo and here are our (mine combined with my CTO's inputs) comments/impressions. While the generation of additional tests/filling holes is a critical piece of its features, I believe the coverage analysis feature is not so well published/well understood.

With our customers who are serious about coverage, the analysis of coverage holes has been one of the biggest pains. The sad part is no major EDA vendor is really adding features to enhance that, with Nusym addressing that problem, it is certainly very useful. The techniques they showed in their slides/demo are not truly path breaking but simple ones that can aid in not wasting time with unreachable coverage holes. It is that simplicity that made me very interested in their stuff. But it is unclear if the tool can go beyond the "static analysis" part and offer more sophisticated means to analyze/exclude coverage holes.

While the major EDA vendors claim to address this challenge, much is yet to be done with say minor changes to RTL, then the whole analysis goes invalid and has to be repeated - much manually. It will be great if Nusym can address that.

The other not-so-much-spoken feature is their "replay" technique - perhaps it is still maturing, but sure enough it is one of those very useful techniques in regression runs.

Thanks and Regards,

Shalini Pandey

CVC Pvt Ltd

What are your painpoints with SystemVerilog ABV adoption?

2009-12-08T08:53:00.001-08:00

While there is so much talk about ABV in the market, the adoption is still far less than desired/expected by the buzz! Harry Foster from Mentor tries to find some rationale in his new blog at:

http://blogs.mentor.com/verificationhorizons/blog/2009/12/06/abv-and-people-from-missouri/#comment-6

Here is what we from CVC feel about it (also added as comments in that blog).

>> What are the obstacles you see to adoption?

Major one I hear from RTL folks often is the verbosity associated (as of SystemVerilog 2005) with using OVL-like libraries. Especially existing users of 0-in checkerware are so much pampered by the ease of use and the value it adds - though their management may have the extra $$ as concern - it is hard for them to appreciate the need to type-type-type the “clock, reset” mundane stuff! It was all being “inferred” so far and suddenly come a standard language/implementation such as SVA and that takes them back in history! Refer to AMD’s excellent presentation on OVL TC for a proof! True, the new (very new I must say) “checker” construct along with $inferred* takes care of it (sigh… it lacks $inferred_enable). We cover these in our recently published SVA Handbook 2nd edition (http://www.systemverilog.us/sva_info.html) and also in upcoming DVCon 2010 paper.

Cheers
Srini
http://www.cvcblr.com

What do you have to say? Please comment, your views will hopefully help in shaping up future SystemVerilog standard!

Adv VHDL Testbench training - Aldec-South Asia begins with a BANG!

2009-12-08T08:33:00.001-08:00

For those who missed it, see:

http://www.aldec.in/Company/News.aspx?newsid=34678573-19e6-45a3-99d5-9d5b6accda6c

This is a significant move I would say as it reinforces few facts:

Industry is slowly recovering (Hurray!!)
India/SouthAsia is gaining more and more importance as a wide customer base – apart from major EDA vendors, others are setting up their own centres, driving investments etc.
India as such provides a vibrant FPGA market and there is enough to tap onto it for EDA vendors!

Recently Aldec-SA conducted a 2-day seminar on “Creating efficient Testbenches using VHDL”. CVC did the delivery of this seminar, being VHDL & Verification experts.

We got very good feedback from this event, here is a sample:

**** Straight from customer ************

Hello Sir,

I am Ramesh R Nair, working in Continental Automotive as an ASIC verification engineer as part of my internship programme of M.Tech(VLSI).

I have attended your training class on test bench writing last week(ALDEC).

Although we are writing a lot of test benches some utilities were unnoticed.. you bring those things to light.

So it was very helpful and i shared it with my team members.

Thank you and Congratulations.

Best Regards

Ramesh R Nair

Continental Automotive Components

Bangalore

*****************************

It is always great to hear feedback from customers and it gets better if it is a positive one :-)

What’s wrong with the present ABV promotion?

2009-12-02T07:24:00.001-08:00

If you have not heard of the buzz word “ABV” (and assuming you are a VLSI front-end engineer of-course) you must be living in a different world I must say (no pun intended) – with so much marketing around it is hard to have missed it – with SystemVerilog Assertions, PSL, OVL etc.

Despite that there are some folks who say the adoption is not as much as predicted – heard it from Adam Sherer earlier this week here in Bangalore and now read it on: http://www.edadesignline.com/showArticle.jhtml?articleID=221901260

Well I for one don’t believe this is fully true – atleast in India/AsiaPac – CVC has done well with ABV, we have developed PSL based MIP (Monitor IP) for Taiwan customers, got paid, and delivered several customer trainings on it etc. Though the recent focus has been more on OVM/VMM/VSV – SVA is still making money I must say. It is entering FPGA domain well, see recent ModelsimDE release, Active-HDL supporting ABV for long time now for FPGA domain etc. And just today we introduced PSL to a large customer base (VHDL house) and it is well received among engineers.

But – yet I agree to some extent, there are challenges with it – that prevents it becoming “Mainstream”. For one we don’t have good tool support to verify Assertions standalone. There were early starts with “Assertion Studio” http://www.systemverilog.org/pdf/AT_HDL_Symposium.pdf but it is no longer to be found! This is to say – I don’t have RTL, no TB, just write SVA/PSL – can I visualize/verify them standalone? Formal tools can in principle do it, I have seen it with Magellan whilst at SNPS, but internally. Not sure if IFV can do it, Jasper can do it etc. Even if they do – it is too expensive an option I guess!

Secondly – I believe there is a lack of good “reference” – to common “templates”. We tried addressing it in our SVA book via dictionary, but being a big book not sure how many used that part of the book. Didn’t hear much from customers on that.

While doing trainings I always felt this would be a perfect fit for an animation based demo/training, tried prototyping it with a publishing house, effort dried off due to lack of commitments/funds. Also – all said and done, the language features as they exist are INADEQUATE to express temporal behaviors intuitively. This is even with SVA-09 features. If I were to re-design a language for it (read it as: if I had all the time and money needed for it) I would develop a from-scratch, user driven means for it, than language/tool imposed restrictions dominating the definition. Just a sample:

“Variable delays” are not allowed in SystemVerilog Assertions – give me a break…(No I don;t need a work-around, I can send you if needed, drop me an email).

Sub $5000 high-end Mixed HDL simulator - VHDL+Verilog+SV-Design

2009-12-01T08:54:00.001-08:00

http://edageek.com/2009/11/16/vhdl-verilog-xilinx-secureip/

Not a bad news after all – given that the industry is showing signs of recovery, such offerings are GREAT indeed – during the downturn several mergers, IP accumulation, consolidation have happened. That might have led to mix of languages in new SoCs. Usually the cost of ownership of a full fledged Mixed-HDL simulator (from any of 3 big EDA vendor) costs a lot (some say a “fortune” though I disagree). But this Riviera offering is certainly encouraging indeed.

But is this a “sign-off” tool? Anyone?

And BTW – in DAC they announced $1995 package for Active-HDL with similar support, so it is real!

http://www.aldec.com/Company/News.aspx?newsid=c86c2ee8-5490-4eae-b61e-a7c0aaf7396c

Sub $5000 high-end Mixed HDL simulator - VHDL+Verilog+SV-Design

2009-12-01T08:37:00.001-08:00

http://edageek.com/2009/11/16/vhdl-verilog-xilinx-secureip/

But is this a “sign-off” tool? Anyone?

Hardware Emulation becoming more and more affordable

2009-12-01T08:31:00.001-08:00

Read: http://www.your-story.org/eve%E2%80%99s-latest-emulator-offers-the-lowest-cost-of-ownership-in-the-industry-62042/

With the so called “penny-per-gate” pricing – sure is a marketing gimmick, it is becoming more and more viable to explore low cost emulation stuff. We still see that our customers continue to rely on own, self cooked FPGA boards, but with such innovative business models it may be changing soon..

Good job Eve folks – I wonder if they allow sharing “across customers” – say we host one Zebu server at CVC and allow several customers to log-in and pay-per-use!

Update on IEEE 1800-2009 standard, fresh from the oven!

2009-11-29T20:02:00.001-08:00

As you all may know by now, IEEE 1800-2009 was recently approved.
There were many updates in SystemVerilog core, the Assertions, and the addition of the checker, a new type of entity where several assertions and verification code can be defined just like a module/interface. In addition the checker can be inlined procedurally unlike a module.

Immediate next step will be to get real users exposed to the power of new constructs. We would expect tool vendors to start adopting this new version, probably sooner than we may think as some vendors were actively implementing the new features as the LRM was being refined. Now atleast 2 major EDA vendors have released support for varying sets of constructs from this new LRM. Ping your EDA support for updates!

As far as book support, we're please to announce the release of our SystemVerilog Assertions Handbook, 2nd Edition that includes the IEEE 1800-2009 updates.
For more information, see http://systemverilog.us/sva2_toc_preface.pdf
http://systemverilog.us/sva_handbook2_cover.jpg

SystemVerilog Assertions Handbook, 2nd Edition is an excellent reference for learning the basics of the assertion language. Syntax summaries along side examples help in learning the syntax. There are many examples with graphical representations that demonstrate the concepts. Basic rules are listed, often with quotes from the standard, and then explained. The book goes beyond the standard to demonstrate many subtleties that produce unexpected results and poor performance, and flags the pitfalls to avoid. It is a great refresher for experienced users and for those looking to understand what is new in the SVA language for the IEEE 1800-2009 release. Additional chapters present methodology and application perspectives. This book is co-authored by:
Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari, and Lisa Piper

Training on “Protocol Verification using SystemVerilog Assertions”

2009-11-24T20:56:00.001-08:00

December is usually the time of holidays, relatively work load etc. Given the challenging job scenario this is also the best time to hone your skills and face the New Year with new skills, explore new job avenues, segments etc.

CVC is announcing a week long certificate course on standard protocol verification. At the end of this course you would have finished developing a MIP (Monitor IP) for a standard protocol based on SVA. Assertions are very powerful to capture temporal behavior. Broadly it covers the following topics:

ABV Introduction
SystemVerilog Assertions (SVA)
Project – develop a real life Protocol Monitor IP (MIP) with SVA

Course contents: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf

Topic	Duration
SystemVerilog Assertions	2.0 days
Project	3.0 days

Schedule

Tentative: 2^nd week of December, 2009

For exact schedule visit http://www.cvcblr.com/blog/ or contact us.

Contact

Send an email to: training@cvcblr.com and/or cvc.training@gmail.com for more details, cost etc. Or call us at: +91-9620209226/+91-80-42134156

Please include the following details in your email:

Name:

Company Name:

Contact Email ID:

Contact Number:

Make best use of your Dec holidays: Verification Fest (VFest)

2009-11-24T20:55:00.001-08:00

CVC is launching its highly successful 2 weeks certificate course on Functional Verification using SystemVerilog with a project in one of the following domains.

· Networking

· Communication

· Image Processing

VFest also focuses the language aspect SV in depth. Broadly it covers the following topics:

SystemVerilog basics (SVB) http://www.cvcblr.com/trng_profiles/CVC_LG_SVD_profile.pdf
Verification Using SystemVerilog (VSV) http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf
Verification Methodology (VM)

Duration

Topic	Duration
SystemVerilog Basics	0.5 day
Verification using SystemVerilog	2.5 days
Mini Project	2.0 days
Verification Methodology	2.0 days
Project	3.0 days

Schedule

Tentative: 1^st week of December, 2009

For exact schedule visit http://www.cvcblr.com/blog/ or contact us.

Contact

Send an email to: training@cvcblr.com and/or cvc.training@gmail.com for more details, cost etc. Or call us at: +91-9620209226/+91-80-42134156

Please include the following details in your email:

Name:

Company Name:

Contact Email ID:

Contact Number:

SystemVerilog tip: watch out enum and randc

2009-11-24T20:54:00.001-08:00

Recently an interesting question was raised by SystemVerilog user on randc usage with enum. To illustrate, consider the following code:

[cpp]
typedef enum {red, green, blue, yellow, white} house_color_type;
class c;
randc house_color_type enum_0;
[/cpp]

Spot anything wrong above? Perhaps not? As it goes with randc an implementation needs to remember all values generated so far before recycling! So it does consume extra memory. SV LRM says:

To reduce memory requirements, implementations may impose a limit on the maximum size of a randc
variable, but it shall be no less than 8 bits.

By default an enum is an int – i.e. 32-bits, hence allowing a randc on it blindly is a real challenge for tools – though some advanced tools/versions (Questa 6.5a for instance) allows it. But this default int choice is not something I like so much – it should have been cleverer to choose appropriate sized of vector by the implementation, did we not know LRM committee is often biased by implementers. No pun intended, but just MHO.

Anyway coming back to the question, a very useful tip here (like “Moral of the story is..” – something that’s day-to-day phrase in a typical school boy father’s life , something that I thoroughly enjoy, thanks to my Anirudh Pradyumnan): Model your enum size while declaring it. As in:

[cpp]

typedef enum {red, green, blue, yellow, white} house_color_type;

typedef enum bit [2:0] {red, green, blue, yellow, white} house_color_type_BETTER;

[/cpp]

ASIC Design Verification for FPGA designers

2009-11-24T20:53:00.001-08:00

…Step upto ASIC world with SystemVerilog, Assertions & Testbench

CVC (www.

Technorati Tags: trainings

cvcblr.com) is announcing a new session of its 10-day course on “FPGA-2-ASIC_DV-with SystemVerilog” - a step-by-step approach to introduce modern day Design & Verification challenges & solutions for FPGA designers. It is structured as follows:

Basic Session
- Comprehensive Functional Verification (CFV)
- SystemVerilog basics (SVB)
Advanced Session
- ABV Introduction
- SystemVerilog Assertions (SVA)
- Project – develop a real life Protocol IP (PIP) with SVA
- Verification Using SystemVerilog (VSV)

Course contents:

http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf

http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf

Topic	Duration
Comprehensive Functional Verification (including UNIX usage, EDA tools)	1.5 days
SystemVerilog basics	1 day
Project	0.5 days
SystemVerilog Assertions	2 days
SystemVerilog Testbench	2 days
Project	3.0 days

All the course contents, agenda can be found at http://www.cvcblr.com/program_offering. It is meticulously prepared with the common expertise of FPGA designers in mind. Having transformed several FPGA designers into ASIC Design-Verification engineers at CVC we fully understand the challenges involved, skills needed etc. The course is structured in a balanced manner with theory and lab sessions tightly embedded in a manner that helps in mastering topics learned so far in the course.

Schedule:

Dec 1^st week at Bangalore

To attend this class, confirm your registration by sending an email to training@cvcblr.com

Ph: +91-9620209226, +91-80-42134156

Please include the following details in your email:

Name:

Company Name:

Contact Email ID:

Contact Number:

SV: implication constraint and its implication/effect

2009-11-08T08:15:00.001-08:00

SystemVerilog has a nice implication constraint feature to guard constraint expressions on their applicability. Last week during our SystemVerilog + methodology workshop one of the attendees faced an interesting issue. She was creating a min-VIP for APB as part of our SystemVerilog 10-day workshop (See details at: http://www.cvcblr.com/trng_profiles/CVC_VSV_WK_profile.pdf ).

She wrote a APB scenario code that was intended to create a sequence of transactions with varying address, kind etc. Here is a code snippet:

constraint cst_xactn_kind{
       if(this.scenario_kind == this.sc_id)
       this.length == 10;
       foreach (items[i])
        {
          (i==0) -> items[i].apb_op_kind == APB_WR;items[i].addr == 'b01; items[i].wdata == 'd11;

               (i==1) -> items[i].apb_op_kind == APB_WR;items[i].addr == 'b11; items[i].wdata == 'd12;
                       }
     }

Spot anything wrong in the above code? Perhaps not for the unsuspecting, bare eyes. Code intention: Keep the:

0th transaction KIND == WRITE, address == 01, data == 11;

1st transaction KIND == WRITE, address == 3, data == 12;

Read again the code – it seems to imply just that, isn’t it? Let’s run it.

Here is what Questa says:

###########################################################################
#                     WELCOME !!!
#                      APB PROJECT USING VMM
#                     DONE BY PRIYA @ CVC
#                     DATE:21stOctober2009
############################################################################
# Normal[NOTE] on APB_PROGRAM(0) at                    0:
#     APB PROJECT:       Start of APB Random test!
# ****************************************************************************
# Normal[NOTE] on APB_ENV(0) at              0.00 ns:
#     APB PROJECT: Sim shall run for 10 number of transactions
# Normal[NOTE] on APB_ENV(0) at              0.00 ns:
#                     Reset!!!!!!!!!
# Normal[NOTE] on APB_ENV(0) at            230.00 ns:
#                    Reset Release!
# ****************************************************************************
# *FATAL*[FAILURE] on APB Generator Scenario Generator(APB_GENERATOR) at            730.00 ns:
#     Cannot randomize scenario descriptor #0

Puzzled? What is wrong? Review by the code author herself few times didn’t reveal anything wrong (bias towards own code?).

Seek expert assistance.. Questa has a simple flag to bring up solver debugger as: vsim –solvefaildebug Let’s try that now..

# ../tb_src_scenario/apb_scenario_gen.sv(1): randomize() failed due to conflicts between the following constraints:
#     ../tb_src_scenario/apb_scenario_gen.sv(25): the_scenario.cst_xactn_kind { (the_scenario.items[0].addr == 32'h00000001); }
#     ../tb_src_scenario/apb_scenario_gen.sv(1): the_scenario.repetition { (the_scenario.repeated == 32'h00000000); }
#     ../tb_src_scenario/apb_scenario_gen.sv(25): the_scenario.cst_xactn_kind { (the_scenario.items[0].apb_op_kind == APB_WR); }
#     ../tb_src_scenario/apb_scenario_gen.sv(26): the_scenario.cst_xactn_kind { (the_scenario.items[0].addr == 32'h00000003); }
#     ../tb_src_scenario/apb_scenario_gen.sv(26): the_scenario.cst_xactn_kind { (the_scenario.items[0].wdata == 32'h0000000c); }
#     ../tb_src_scenario/apb_scenario_gen.sv(26): the_scenario.cst_xactn_kind { (the_scenario.items[1].apb_op_kind == APB_WR); }
#     ../tb_src_scenario/apb_scenario_gen.sv(26): the_scenario.cst_xactn_kind { (the_scenario.items[1].addr == 32'h00000003); }
#     ../tb_src_scenario/apb_scenario_gen.sv(26): the_scenario.cst_xactn_kind { (the_scenario.items[1].wdata == 32'h0000000c); }
#     ../tb_src_scenario/apb_scenario_gen.sv(26): the_scenario.cst_xactn_kind { (the_scenario.items[2].addr == 32'h00000003); }
#     ../tb_src_scenario/apb_scenario_gen.sv(26): the_scenario.cst_xactn_kind { (the_scenario.items[2].wdata == 32'h0000000c); }
#     ../tb_src_scenario/apb_scenario_gen.sv(26): the_scenario.cst_xactn_kind { (the_scenario.items[3].addr == 32'h00000003); }
#     ../tb_src_scenario/apb_scenario_gen.sv(26): the_scenario.cst_xactn_kind { (the_scenario.items[3].wdata == 32'h0000000c); }
#     ../tb_src_scenario/apb_scenario_gen.sv(26): the_scenario.cst_xactn_kind { (the_scenario.items[4].addr == 32'h00000003); }
#     ../tb_src_scenario/apb_scenario_gen.sv(26): the_scenario.cst_xactn_kind { (the_scenario.items[4].wdata == 32'h0000000c); }
#     ../tb_src_scenario/apb_scenario_gen.sv(26): the_scenario.cst_xactn_kind { (the_scenario.items[5].addr == 32'h00000003); }
#     ../tb_src_scenario/apb_scenario_gen.sv(26): the_scenario.cst_xactn_kind { (the_scenario.items[5].wdata == 32'h0000000c); }

Smell something wrong? Why is the constraint on addr, data getting applied across scenario items 2,3,4,5 etc.? Beyond the 0, 1 that the “implication” supposed to guard it? Relook at constraint code:

(i==0) -> items[i].apb_op_kind == APB_WR;items[i].addr == 'b01; items[i].wdata == 'd11;

Found it? Not yet? The devil lies in details – here in that SEMICOLON “ ; “. A semicolon in Verilog/SV denotes END of a statement and begin of the next one. Hence the effect of “implication” is ENDED with the variable “kind” alone here – thereby it doesn’t affect the addr, data – hence the implication is invisible to them. At line 25, the addr == 1; At line 26, addr == 3; Hence the contradiction!

The fix will be to use && to imply that the guard is applicable to all the 3 variables – kind && addr && data.

Instead of:

(i==0) -> items[i].apb_op_kind == APB_WR;items[i].addr == 'b01; items[i].wdata == 'd11;

Use:

(i==0) –> (items[i].apb_op_kind == APB_WR) && (items[i].addr == 'b01) && (items[i].wdata == 'd11);

Morale of the debug session is: you need to be careful while using implication constraints for more than single variable :-)

Certificate course on SystemVerilog Assertions …Language + Lab + Mini-project

2009-07-07T04:25:00.001-07:00

Certificate course on SystemVerilog Assertions

…Language + Lab + Mini-project

CVC is announcing a new session of its popular 2-day certificate course on SsystemVerilog Assertions (ABV_SVA) covering SystemVerilog Assertions in depth. Broadly it covers the following topics:

ABV Introduction
SystemVerilog Assertions (SVA)
Project – develop a real life Protocol IP (PIP) with SVA

Course contents: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf

Duration

Here is a detailed breakdown of the course with duration. Note that we have a “mini project” tightly embedded in the course that helps in mastering topics learned so far in the course. This is on top of the regular labs that are part of the training.

Topic	Duration	Start	End
SystemVerilog Assertions	1.5 days	July 13	July 14
Mini Project II	0.5 day	July 14	July 14

Schedule:

July 13, 14 at Bangalore

To attend this class, confirm your registration by sending an email to training @ cvcblr.com

Ph: +91-9916176014, +91-80-42134156

Please include the following details in your email:

Name:

Company Name:

Contact Email ID:

Contact Number:

CCD, My read of Certess technology and positioning

2009-03-14T11:52:00.001-07:00

With due respect to the technology behind Certess’s tool I have some discomfort with the way it is being positioned – atleast in the below article:

http://www.edadesignline.com/howto/215600203;jsessionid=TP12OA3IF1X3UQSNDLOSKHSCJUNN2JVN?pgno=2

Before I talk about my discomfort, let me state the positives: Not very often do we get to read such well written, all encompassing technical article, Kudo’s to Mark Hampton – he touches on every aspect of functional verification in this article, not so common in an EDA product “promotional” article – to which this article may be characterized to (unfortunately IMHO). Having said that, I personally believe Certess should position the technology “along with” existing ones than challenging/trying to replace time tested/well adopted methodologies such as code cov, functional cov etc. Not that I differ from his views on the shortcomings of these technologies, rather going by what Pradip Thakcker said in DVM 08 (http://vlsi-india.org/vsi/activities/2008/dvm-blr-apr08/program.html)

“Code coverage and functional coverage are useful techniques with their own strengths and weaknesses. Rather than worrying about their weaknesses, focus on the positives and use them today”..Pradip, during his “Holistic Verification: Myth or The Magic Bullet?”

I will be very glad if Certess focuses on their real strength of exposing lack of checkers in a Verification environment than trying to “eat” into the well established market of Code/Func coverage tools. Another rationale: Both the cov and qualification is compute intensive and given the amount of EDA investment that has gone into stabilizing and optimizing these features, it will be irrational to try and replace them with “functional qualification” (No offense meant, I have great respect for Mark – given his excellent article and ofcourse the product). With SpringSoft acquiring Certess hopefully their customer base/reach increases and that will throw up more success stories in the coming months/quarters. So good times ahead!

ITG, C2D & ACC - Emerging Verification technologies

2009-03-14T11:43:00.001-07:00

Well, it is not the overly hyped *V here - such as CRV, CDV, ABV - we at CVC (www.noveldv.com) consider them as yesterday-ones for the sake of giving room to next generation ones such as:

ACC - Automatic Coverage Closure
ITG - Intelligent Test Generation (such as Graph based)
CCD - Covered & Checked implies Done (such as Certess/SpringSoft)

Out of this let me spend more time on the last two as the ACC is already been discussed for a while now (atleast more than the other two).

ITG - Intelligent Test Generation (such as Graph based)

ITG - is still in its early days. Two tools seem to be addressing this as of today:

Infact from Mentor is one big name.
The other one that is very promising is: Breker Systems with a very high profile team behind it. These folks know what they are talking about - with their CTO holding "Adnan holds 15 patents in test case generation and synthesis.".

We at CVC are yet to get our hands dirty with these tools, but certainly worth watching indeed! From our early analysis this technology will assist more and more system level tests being easily captured by raising the level of abstraction of testcase specification. This will be fun indeed!

CCD - Covered & Checked implies Done

Coming to the other category: CCD (yet to find a better name) – this is a topic that has been haunting us for atleast a decade now. Ever since I started using Functional coverage (early 2000), we always had this problem of “I got it covered, but did I get it checked too?”. During an Ethernet monster switch/router verification at Intel we hit this problem atleast half-a-dozen times and those corridor discussions still ring in my ears. The Design (read it as RTL) manager (Sutapa Chandra) made fun of us asking “are we taping out RTL or testbench” as we seem to be finding lack of checkers every now and then. Most of these situations are the case of bugs went undetected at block/cluster level and later get got (luckily) at full chip level – then we do a rigorous review of our block level env, and find that we indeed had coverage points for those scenarios, just that we didn’t have enough checkers! Shame, but true. A technology such as Certess’s Testbench Qualification was what was indeed needed! A very detailed read of Certess technology is at: http://www.edadesignline.com/howto/215600203;jsessionid=TP12OA3IF1X3UQSNDLOSKHSCJUNN2JVN?pgno=2

OVM rule checker for free!

2009-03-06T10:21:00.001-08:00

A process/methodology is only as good as its adoption/compliance. And in Verification since there are so many different ways of “getting it done” it is hard to get sync across teams/groups/projects/companies etc. This is where the methodology comes to play (be it VMM,OVM<eRM etc.). But again how am I sure that I follow all the guidelines?

Consider this – we got an email from a user as recently as last week on our VMM book code (www.systemverilog.us) about not adding “is_valid” method in data model. The book was published back in 2006 I believe. That just goes to say that a “compliance checker” is a very handy tool to create highly reusable Verification code. But who will check for compliance?

Thankfully, here is an answer for OVM and that too for no cost!

http://www.veriez.com/dvcon_2009_pr.htm<a href="http://www.veriez.com/dvcon_2009_pr.htm"></a> This is indeed an interesting development and a welcome one during tight economical situations. Make sure you download and use them!

Cheers,

Ajeetha www.noveldv.com

Automatic Coverage Closure – my perspective

2009-02-18T04:02:00.001-08:00

Recently EDA tools are emerging in the area of “Automatic Coverage Closure” that promise a new level of automation in CDV/MDV/any_other_Buzz_word_Driven_Verification process. A significant name in this arena is nuSym, a relatively new EDA player. There have been few good reviews about them @ Deepchip.com.

http://deepchip.com/items/0479-05.html

http://deepchip.com/items/0473-06.html

http://deepchip.com/items/dvcon07-06.html

And another one @ SiliconIndia:

http://www.siliconindia.com/magazine/articledesc.php?articleid=DPEW289996212

And very recently on VerifGuild:

http://www.verificationguild.com/modules.php?name=Forums&file=viewtopic&t=3102

I like Gopi’s post/comment b’cos I have the same opinion about CRV (Constraint Random Verification) – it catches scenarios/bugs that you didn’t envision – either via constraints or coverage (or otherwise). Now if we fool ourself by going behind “only the existing/identified coverage holes” we fall into a trap. This is inline/insync with what Sundaresan Kumbakonam of BRCM ( need his profile? See: http://vlsi-india.org/vsi/activities/dvw05_blr/index.html) shared with me once:

Quoting Sundaresan:

I don’t believe much in the idea of “writing functional coverage model” and then tweaking a constraint here-or-there, or writing a “directed test” for it to fill the hole.

Coming back to my view, I believe some redundancy via randomness/CRV is actually good. In my past verification cycles I have seen design errors due to “repeated patterns” – no big deal, is it?

So where exactly do these ACC tools fit?

Referring back to:

http://www.verificationguild.com/modules.php?name=Forums&file=viewtopic&t=3102

>> whether these tools are only used to reach last few % of coverage goal which is hard to reach ?

I would differ here, they shall be very useful somewhere during the middle phase – neither too early, nor too late. Too early – perhaps we don’t have full RTL and/or functional cov model. Too late – perhaps our focus should be more into “checking” than only coverage (As Nagesh pointed out in VerifGuild). I would like to add that during those last minutes, the coverage shall be taken for “granted” – meaning it is a *must* and not a *nice to have* thing and the focus shall be to look for any failures.

To me a reasonable flow with these ACC tools would be:

Run with CRV, measure code coverage. Add checkers
Add functional coverage, use CRV again to hit them using the coverage points as “potential trouble spots” than “actual scenarios” themselves. In few cases where in the scenario description is easy to capture using Functional coverage syntax, this is great. IMHO the existing coverage syntax is little too verbose and unusable to a large extent for solid, easy-to-use coverage specification. Specifically the SV syntax overhead of coverage is just too much for me. IEEE 1647 “e” fairs slightly better but that’s a different story altogether. I’m still on the lookout for a higher level coverage specification language.. (matter for another blog post anyway).
Once the RTL and the coverage model is reasonably stable, use ACC regularly as a “sanity” test on every interim RTL release. I believe ACC has a HUGE potential here – if we can optimize the tests needed to release interim RTL versions, we are saving quality time and enabling faster turn around.
Towards the end, enable “plain CRV” (without the ACC bias) and look for “trouble free regression for XX days”.

And while speaking to a friend of mine here a while back, he is damn against the idea of using these ACC tools for merely stimulus. He likes the idea of ACC if it can be used to:

Fill functional cov holes
Code coverage holes
Assertion cov misses/holes

A tough ask, but looks like nuSym can handle that – atleast based on the early reviews so far. Also reading their whitepaper on “intelligent verification”, they do a path tracing that enables them to systematically target code coverage without getting into Formal world – cool idea indeed! Kudos to nuSym folks (some of them my ex-colleagues BTW).

And on the application of these ACC tools to the poor, non-CRV/CDV folks – there is light at the end of the tunnel, if you read nuSym’s paper. We at CVC also have ideas on how to use this for a highly configurable IP verification with plain vanilla verilog/task based TBs. We need to prototype it before we can discuss it in detail though.

Anyway, good topic for otherwise a downturn mood.

More to follow.

Srini

P.S. Sorry for the “random” rambling, after all we are talking of “random verification” :-)

Certificate course on Functional Verification …basics to ASIC verification using SystemVerilog

2009-02-11T05:16:00.001-08:00

Certificate course on Functional Verification …basics to ASIC verification using SystemVerilog

CVC is about to launch a 10-day certificate course on Functional Verification covering SystemVerilog in depth. Broadly it covers the following topics:

Comprehensive introduction to Functional Verification (CFV)
SystemVerilog basics (SVB)
SystemVerilog Assertion (SVA)
Verification Using SystemVerilog (VSV)
Verification Methodology (VM)

Duration

Here is a detailed breakdown of the course with duration. Note that we have several “mini projects” tightly embedded in the course that helps in mastering topics learned so far in the course. This is on top of the regular labs that are part of the training. The detailed breakup of topics and labs is covered in next sections of this proposal.

Topic	Duration
Comprehensive Functional Verification	1.5 days
Mini Project I	0.5 day
SystemVerilog Basics	0.5 day
SystemVerilog Assertions	1.5 days
Mini Project II	0.5 day
Verification using SystemVerilog	2.0 days
Mini Project III	0.5 day
Verification Methodology	2.0 days
Project IV	1.0 day

Schedule

Tentative: Feb 09-Mar09

Contact

Send an email to: cvc.training@gmail.com and/or training@noveldv.com for more details, cost etc. Or call us at: +91-9916176014

When will SV Interface be really useful?

2009-02-09T10:01:00.000-08:00

The idea of adding interface construct to SV language has proven to be a short sighted one with all its ugly ramifications for the RTL side (refer to good papers on this from Jonathan @Douolos if you need proof). Add to it the fact that not all RTL synthesis (+ FPGA), Linters, Equiv. checkers fully supporting it yet!

Atleast on Verification front it has been proving good. However a significant drop has been the lack of proper debug support for it. I wish EDA takes debug seriously. It affects productivity so much that any language level gain we get is nullified with lack or weak support for these new constructs.

For instance, look at SV Interface as a simple "wire bundle" - do we have debuggers handle it at that level of abstraction?

Luckily Verdi seems to be doing it (leading the way as ever before), see:

http://newsletter.springsoft.com/.docs/pg/10768

Happy debugging!

Ajeetha, CVC
www.noveldv.com

Excellent case study on automatic Coverage closure – nuSym & QCOM

2009-02-05T02:19:00.001-08:00

An absolute *must read* for all those CDV/CRV fans (FWIW: CDV – Coverage Driven Verification, CRV – Constrained Random Verification):

http://www.deepchip.com/items/0479-05.html

A live case study from Jim @QCOM. It has good details about the setup, work done and results. Looks like nuSym does deliver the kind of promises/claims it makes, good going indeed! Based on the last 2 such results (both @deepchip.com) I have few observations:

1. Both of them were using Vera against SystemVerilog. While the technology shall be language independent, it will be good to get a SV case study out as well

2. I’m not very clear why and how nuSym can replace a core “simulator” – there are just lot more things in a “simulator” than just “coverage closure/intelligence” – what about debug, stability, memory footprint, gate level/ASIC sign off, dumping, Debussy like integration etc etc.? I fully appreciate the smartness in random generation – it is time EDA folks did that in so called modern “Verification platforms”. But I fail to see how a point tool like nuSym can “replace” a simulator, instead it shall augment it and bring the bigwig EDA vendor pricing down to a reasonable bargain :-)

More notes as we read/re-read that article.

Anyway thanks Jim for sharing those wonderful details!

Cheers

Srini

CTO @CVC www.noveldv.com

SVA challenges in creating, debugging and verifying assertions

2009-02-03T10:30:00.001-08:00

During our SVA class today there were frequent questions/comments on:

How to write assertions easily without becoming a language guru?
How to ensure that the assertions we write are correct to start with? (Not syntax wise, rather functionally)
How to visualize assertions/attempts/threads easily?
Can we create assertions automatically from a timing diagram/dump file?
How to debug assertions? What sort of automation is available?
Given a dump file, can we explore a set of assertions about that design (without having to rerun the simulations)?
Can we verify assertions in isolation – i.e. even before RTL and/or TB is ready?

Sure a boatload of questions, some answers are available some are not as of today. CVC will address some of these in a seminar in one of the coming weeks. (Stay tuned to this site for that news).

Here are some answers:

Q: How to write assertions easily without becoming a language guru?

Leverage on assertion libraries such as OVL, VMM SVA lib, QVL, IAL etc.

Q: How to ensure that the assertions we write are correct to start with? (Not syntax wise, rather functionally)

Not an easy thing, but again use pre-verified assertion lib elements (see prev Q)

Q: How to visualize assertions/attempts/threads easily?

Know your tools: Springsoft (formerly Novas) has a great product called Verdi that can present a “Temporal Flow View” and thread view. It is so amazing and intuitive that you will stay locked with it for long long time to come, really speaking. The idea of temporal annotation is not new, we spoke about it in our PSL book, see below a snapshot:

The core idea is to annotate the values of signals at “appropriate time” and not just based on current time (the latter is what most of debuggers do, except for Verdi AFAIK).

Consider a code like:

mul_attempts : assert property (@posedge clk) start |=> s1;

sequence s1;

a ##1 b ##2 c;

endsequence

Below is a screenshot of how Verdi can display it.

2 key/novel ideas here to appreciate:

1. The threads are nicely displayed with “horizontal lines” – this is exactly how our PPT in training explains threads BTW!

2. The Temporal annotation of the sequence/property with values & time stamps. For the failure at 350 ns (assume 20 ns clock period), it shows value of: (a ##1 b ##2 c;)

“c” @350ns
“b” @310 ns
“a” @290
“start” @270ns

This is simply superb, hats off to Verdi!

Q: How to debug assertions? What sort of automation is available?

Refer to prev Q, almost every vendor provides some automation.

Q: Can we create assertions automatically from a timing diagram/dump file?

Yes, there have been few attempts at this. OneSpin claims this feature and also a new start-up http://solidoaktech.com/TD2Assert.html We will investigate more and update here soon.

Q: Given a dump file, can we explore a set of assertions about that design (without having to rerun the simulations)?

VCS can do this
Springsoft/Verdi can do this
Veritools can do this too!

Q: Can we verify assertions in isolation – i.e. even before RTL and/or TB is ready?

Strictly speaking this is ideal job for formal verification tools. We believe some tools such as Magellan (Synopsys) already do this. We will update more here, stay tuned (for the 3rd time in this post…)

Week long fest on Verification Using SystemVerilog - Bangalore

2009-02-01T09:30:00.001-08:00

Quick facts
When: Feb 2 to Feb 6 2009

Cost: Rs. 5000 /- per day

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-42134156

What’s SystemVerilog?
IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.

What’s a week long fest?
A week long fest on SystemVerilog for Verification is aimed at introducing SystemVerilog in its full capacity covering basics, assertions, testbench features and ending with methodology. At the end of this fest the essential features of SystemVerilog shall be covered and will enable you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. It is aimed at novice SV users and hence language is dealt with a target DUT in picture. The goal is to put SV to use for real life verification than understand the nitty gritties of the language from semantic/gotchas perspective.

Who should attend?
Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV. Though it is strongly recommended to attend the whole 5 day fest, some may choose just the assertions/testbench/methodology and be present in those days accordingly. Please call use for more details.

Tools used

Questa/Modelsim (Mentor)
VCS (Synopsys)
Riviera (Aldec) - optional

What’s the cost?
The basic cost of this course is Rs. 5,000 /- + ST (12.36 %) per day per attendee.

Terms & Conditions
· In general we require that the fee is paid in 100% prior to the start of the training.
· For large corporate with more number of attendees to account for their internal process we do allow an exception to the above rule; however we charge an additional 25% of the training cost per attendee in such cases. In case the fee is paid after the training, the payment should be made within 1 week after the training is delivered. Any additional delay shall be charged at 10% every additional day.
· Any "offer" price mentioned in the course announcement is applicable only for individual attendees and not for corporate.

Cancellation Policy
Course tuition is fully refundable up to one week before the class starts. Cancellations within a week (2-7 days) of the class start date will incur a 50% cancellation fee. Those who cancel fewer than 2 days prior to the class will be billed for the full amount of the tuition. A no-show will be treated as cancellation and no refund shall be given. For genuine cases of absence, we can provide a training token that the trainee can avail in one of the future training classes subject to space availability.

How do I register for a class?
To attend this class, confirm your registration by sending an email to cvc.training @ gmail.com. +91-9916176014, +91-80-42134156

Please include the following details in your email:
Name:

Company Name:

Official Email ID:

Contact Number:

Trainer Profile

Srinivasan Venkataramanan, CTO

http://www.linkedin.com/in/svenka3

Over 12 years of experience in VLSI Design & Verification
Co-authored leading books in the Verification domain.
Worked at Philips, Intel, Synopsys in various capacities.
Presented papers, tutorials in various conferences, publications and avenues.
Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV and OOP for Verification
Holds M.Tech in VLSI Design from prestigious IIT, Delhi.

Ajeetha Kumari, CEO & MD
· Has 8+ years of experience in Verification
· Co-authored leading books in the Verification domain.
· Presented papers, tutorials in various conferences, publications andavenues.
· Worked with all leading edge simulators and formal verification(Model Checking) tools.
· Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDVand OOP for Verification
· Holds M.S.E.E. from prestigious IIT, Madras.

SV care-abouts with disable iff construct

2008-10-24T08:11:00.000-07:00

During our SystemVerilog Assertions handbook writing, we identified a set of guidelines for effective coding of complex, scalabe properties.

Some of them have to deal with handling abort conditions during a property evaluation. In any practical protocol used to transfer data across, typical transfers occur over several clock cycles. There are situations where-in an abort condition triggers and ongoing evaluations needs to be aborted/terminated. IEEE 1800 SystemVerilog provides disable iff construct to model this. A sample code:

Now consider the case that the aborting condition is not a simple signal, rather a temporal sequence. One might think of adding a sequence inside disable iff but that's illegal as per LRM. You typically get errors like:

// Tool errors out
// See: http://www.verificationguild.com/modules.php?name=Forums&file=viewtopic&t=2889

Sequence or property instance used in a non-temporal context
//

So how do you model an abort sequence then? Consider a temporal behavior being verified as shown below:

Now consider an abort sequence as in:

So how do you model this? SystemVerilog allows sequence.triggered inside disable iff. So you can do:

a_p_mstr_xfer : assert property (disable iff (mstr_abort_seq.triggered) p_mstr_xfer);

Enjoy SystemVerilog!

Ajeetha, CVC
www.noveldv.com

Free Seminar on "Quest for Scalable Verification => result:Questa + OVM "

2008-07-22T21:43:00.000-07:00

Free Seminar on "Quest for Scalable Verification => result:Questa + OVM "

With ever growing complexities of ASICs (and FPGAs), the task of verifying them has become a “never-say-done” activity. Given the need for multiple levels of reuse in design and verification, a stand-still approach to verification doesn’t hold good any longer. It requires continuous inflow of new ideas, thoughts and technologies to address the complex requirements. Hence the quest for a scalable verification has been a continuous one. A series of innovative, path breaking technologies have emerged over the last decade to address the verification challenges. Back in 2005 IEEE standardized SystemVerilog as the standard HDVL to incorporate many of these technologies with a Verilog flavor. Since then SV has been making its way into being the most preferred language for ASIC Design and Verification across the globe. However leading edge semiconductor houses have quickly realized that using SystemVerilog on its own might lead to sub-optimal benefits especially in Verification. This is due to the fact that the language is vast and not every team has enough time to experiment with the right usage model for the task at hand. This is the primary motivation behind adopting a Verification Methodology - to get more productive in less time.

OVM as announced in late 2007/early 2008 is proving to be a very good choice for building such scalable verification infrastructure as it has all the classical methodology features plus some of the most advanced, proven verification techniques such as Virtual sequences, factories etc. The good thing about OVM is it is open, and there is a vibrant ecosystem building around OVM. We at CVC have an everlasting thirst to be on top of any new verification technology. As part of Mentor’s Questa Vanguard program, CVC has had the privilege of experiencing the power of OVM early with a robust, easy-to-use verification platform – Questa!

As with any new technology, the initial adoption requires some ramp up time. During our early engagements with building OVM compliant verification environments we went through a series of learning steps. As a result of it, we at CVC recently composed a step-by-step OVM quick start guide that we share with our customers. In this seminar, we share an early preview of this step-by-step guide with a simple packet de-serializer design. We walk through the following topics:

SystemVerilog features for Verification
OVM introduction
DUV - Packet de-serializer
Step-by-step OVM approach with code snippets
Highlights of important Questa features that helped us in the process
Results, summary and looking forward

To attend this seminar: Click on: Register for CVC OVM with Questa seminar. If the above link doesn’t work, send an email to mailto:cvc.training@gmail.com;?subject=CVC_OVM_Questa Please include the following details in your email.

Name:
Company Name:
Official Email ID:
Contact Number:

Venue: CVC Bangalore Office (Ground Floor)

Date: 2^nd Aug 2008, Saturday at 15.00 (3.00 PM)

Agenda: 1 hour presentation followed by a quick demo + Q&A

Bangalore, July 23rd: Free seminar on: Advanced Verification with Aldec’s Riviera-PRO - with SystemVerilog

2008-07-18T08:27:00.000-07:00

Advanced Verification with Aldec’s Riviera-PRO

Given the ever growing complexities of SoC designs, the task of verifying these SoCs is herculean indeed! A series of innovative, path breaking technologies have emerged over the last decade to address the verification challenges. Industry is seeing a culmination of these techniques in the form of new languages such as IEEE 1850-PSL, IEEE 1666 SystemC etc. Every language provides a complementary strength, and addresses specific problem. Recently, many of these separate language capabilities have been integrated into single language and are available as IEEE-1800 standard SystemVerilog (SV). SV is poised to be the choice of DV engineers for many years to come due to the overwhelming support from all tools and the greater eco-system of trainings, books and papers.

Aldec has been the primary EDA provider for various ASIC and FPGA design tasks for 24 years by now. Riviera-PRO is a proven high-performance, mixed-language simulation engine with advanced debugging tools for ASIC and FPGA design teams. Riviera-PRO supports VHDL, Verilog®, SystemVerilog, SystemC, C/C++, PSL and OVA assertions from one common design environment. Riviera-PRO enables mixed RTL debugging, long regression testing, timing simulation and electronic system level (ESL) verification.

IEEE 1800, SystemVerilog is a major extension to Verilog-2001, adding significant new features to Verilog for verification, design and synthesis. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of a
complete Object-Oriented paradigm features. We at CVC have been on the top of leading edge verification technologies for the past half-a-decade. We recently setup an advanced verification environment for a memory controller using SystemVerilog and Aldec’s Riviera-PRO. In this seminar and share that anecdote with the attendees. We walk through the following topics:

· Advanced Verification techniques

· Verification Architecture for Memory controller

· Key SystemVerilog features used in this verification with code snippets

· Screenshots of important Riviera-PRO features that helped us in the process

To attend this seminar, confirm your registration by sending an email to cvc.training@noveldv.com , cvc.training@gmail.com with subject as CVC_Verif_Aldec Seminar. Please include the following details in your email.

Name:
Company Name:
Official Email ID:
Contact Number:

Venue: CVC Office (Ground Floor)

Date: 23^rd July 2008 at 11.00 A.M
Agenda: 1 hour presentation on Advanced Verification Using Aldec followed by demo

Fast-Track course on Verification Using SystemVerilog - Hyderabad

2008-06-30T21:17:00.000-07:00

Fast-Track course on Verification Using SystemVerilog - Hyderabad

Quick facts
When: 12th (or) 13th July (Sat/Sun)

Cost: Rs. 4000 /-

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s a Fast-Track course?
A Fast-Track process is intended to cut short detailed explanations aimed at getting to the core of the subject ASAP. CVC’s Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.

What’s the cost?
The basic cost of this course is Rs. 4,000 /- + ST (12.36 %) per attendee.

How do I register for a class?
To attend this class, confirm your registration by sending an email to cvc.training @ gmail.com. +91-9916176014, +91-80-41495572
Please include the following details in your email:
Name:

Company Name:

Official Email ID:

Contact Number:
Preferred Date: 12th (or) 13th July (Saturday or Sunday)

Are there extended versions of these courses?
Of-course yes! Our flagship trainings on Verification Using SystemVerilog are originally designed for 3 variants:
· 10-day class with extensive labs and a complete project (suitable for students, jobseekers)
· 3-day class and
· 2-day class
So, depending on how much time you can invest, you pick the one appropriate to you. Needless to say – the more time you invest, the better you master this amazingly powerful language.

Trainer Profile

Ajeetha Kumari, Design Verification Consultant
· Has 8+ years of experience in Verification
· Co-authored leading books in the Verification domain.
· Presented papers, tutorials in various conferences, publications andavenues.
· Worked with all leading edge simulators and formal verification(Model Checking) tools.
· Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDVand OOP for Verification
· Holds M.S.E.E. from prestigious IIT, Madras.

Fast-Track course on Verification Using SystemVerilog - Hyderabad

2008-06-23T00:51:00.000-07:00

Fast-Track course on Verification Using SystemVerilog - Hyderabad

Quick facts
When: 13th /14th July (Sun/Mon)
Where: Hyderabad

Cost: Rs. 4000 /-

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s the cost?
The basic cost of this course is Rs. 4,000 /- + ST (12.36 %) per attendee.

How do I register for a class?
To attend this class, confirm your registration by sending an email to cvc.training@gmail.com. +91-9916176014, +91-80-41495572
Please include the following details in your email:
Name:

Company Name:

Official Email ID:

Contact Number:
Preferred Date: 13th or 14th July (Sunday or Monday)

Trainer Profile

Comprehensive Functional Verification (CFV)

This course is a jump start, meant for entry level which is unique of its kind and it covers the aspects of Verification in one day. It provides you the best platform to start a career in Functional Verification. By attending this course you will understand the nuances of FV.

Languages

IEEE 1800 SystemVerilog Design (SVD)
IEEE 1800 SystemVerilog Assertions (SVA)
IEEE 1800 SystemVerilog for Verification (SVTB)
IEEE 1850 Property Specification Language (PSL)
IEEE 1647, e-language
IEEE 1364 Verilog
IEEE 1076 VHDL

Methodology

IEEE 1800 - SV Based Verification Methodology Manual (VMM)
IEEE 1800 - SV Based Open Verification Methodology (OVM)
Assertion Based Verification (ABV)
Coverage Driven Verification (CDV)

Workshops

Gate Level Simulation
ABV beyond RTL
OOP Basics

Fast-Track course on Verification Using SystemVerilog - Bangalore

2008-06-15T06:36:00.000-07:00

Fast-Track course on Verification Using SystemVerilog - Bangalore

Quick facts
When: 19th /20th June (Thurs/Fri)
Where: Bangalore, CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)

Cost: Rs. 4000 /-

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s the cost?
The basic cost of this course is Rs. 4,000 /- + ST (12.36 %) per attendee.

Venue details
CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Date: 2 potential dates:
Friday 20th June at 8.30 AM
Saturday 21st June at 8.30 AM

Company Name:

Official Email ID:

Contact Number:
Preferred Date: 20th or 21st June (Friday or Saturday)

Trainer Profile

Fast-Track course on Verification Using SystemVerilog - Bangalore

2008-06-01T08:02:00.000-07:00

Fast-Track course on Verification Using SystemVerilog - Bangalore

Quick facts

When: 6^th or 7^th June (Fri/Sat)

Where: Bangalore, CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Cost: Rs. 2500 /- onwards (See below for details)

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s SystemVerilog?

IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.

What’s a Fast-Track course?

A Fast-Track process is intended to cut short detailed explanations aimed at getting to the core of the subject ASAP. CVC’s Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.

Who should attend?

Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV in 1-day without bothering about the nitty-gritty in great detail.

What’s the cost?

That is a no-brainer question, isn’t it? We understand and appreciate the cost conscious landscape of our region. That’s why we have innovative cost structure as shown below.

The basic cost of this course is Rs. 4,000 /- per attendee. As a limited period offer, we are glad to announce “The more-the-merrier” scheme. If you pool in more folks you get more discounts. For every other attendee that you bring along, you get Rs. 500 /- discount – for BOTH the attendees (subjected to a minimum of Rs. 2500 /-), can it get better than this :-) ?

Here is a simple table showing the offer in numeric:

No. of attendees | Cost per attendee | Your savings (total)

2 3500 1000

3 3000 3000

4 (and above) 2500 6000+

Venue details

CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Date: 2 potential dates:

Friday 6^th June at 8.30 AM

Saturday 7^th June at 8.30 AM

How do I register for a class?

To attend this class, confirm your registration by sending an email to cvc.training @ gmail.com. +91-9916176014, +91-80-41495572

Please include the following details in your email:

Name:
Company Name:
Official Email ID:
Contact Number:

Preferred Date: 6^th or 7^th June (Friday or Saturday)

Are there extended versions of these courses?

Of-course yes! Our flagship trainings on Verification Using SystemVerilog are originally designed for 3 variants:

· A 10-day class with extensive labs and a complete project (suitable for students, jobseekers)
· A 3-day class and
· A 2-day class

So, depending on how much time you can invest, you pick the one appropriate to you. Needless to say – the more time you invest, the better you master this amazingly powerful language.

Trainer Profile
Ajeetha Kumari, Design Verification Consultant
* Has 8+ years of experience in Verification
* Co-authored leading books in the Verification domain.
* Presented papers, tutorials in various conferences, publications and
avenues.
* Worked with all leading edge simulators and formal verification
(Model Checking) tools.
* Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV
and OOP for Verification
* Holds M.S.E.E. from prestigious IIT, Madras.

VMM is for everyone now!

2008-05-28T08:04:00.000-07:00

One of the most awaited good news for VLSI Verification community is finally here. VMM is free, open and freely downloadable, Voila!!

http://www.vmmcentral.org/home.html

Enjoy VMMing!

Ajeetha, CVC
www.noveldv.com