tag:blogger.com,1999:blog-73437933798686030982024-03-18T20:41:42.312-07:00SystemVerilog for VerificationAjeetha Kumarihttp://www.blogger.com/profile/10099738793915191587noreply@blogger.comBlogger129125tag:blogger.com,1999:blog-7343793379868603098.post-31188059362217894652013-11-06T08:52:00.001-08:002013-11-06T08:52:01.173-08:00Asynchronous events and SVA – a quick primer<p>During our recent SystemVerilog Assertions update webinar (<a title="http://www.cvcblr.com/blog/?p=802" href="http://www.cvcblr.com/blog/?p=802" target="_blank">http://www.cvcblr.com/blog/?p=802</a>) one of the audience raised a question on how to check asynchronous events using SVA. Here comes a quick response with code. Also simulated using Aldec’s Riviera-PRO tool.</p> <p><a href="http://lh6.ggpht.com/-J7Oj_mb2nDQ/Unpzqy904uI/AAAAAAAAA8A/4qXp50CR26k/s1600-h/sva_async%25255B3%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="sva_async" border="0" alt="sva_async" src="http://lh4.ggpht.com/-iBkoQeLrfv0/Unpzrz8GwuI/AAAAAAAAA8I/T5JIsUBk0Zg/sva_async_thumb%25255B1%25255D.png?imgmax=800" width="641" height="399" /></a> </p> <p> </p> <p>As you can see in the picture, no clock involved per-se, but use the start and end events themselves as clock for the SVA. </p> <p>So, if you’ve more challenging requirements, do drop in at <a href="http://www.cvcblr.com" target="_blank">CVC</a> and we will assist you resolve them! </p> <p><a href="http://www.cvcblr.com" target="_blank">TeamCVC</a></p> <p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:219e01f1-abba-4cba-8453-d3b91ac966b6" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/Verilog" rel="tag">Verilog</a>,<a href="http://technorati.com/tags/SystemVerilog" rel="tag">SystemVerilog</a>,<a href="http://technorati.com/tags/SVA" rel="tag">SVA</a>,<a href="http://technorati.com/tags/ABV" rel="tag">ABV</a>,<a href="http://technorati.com/tags/Aldec" rel="tag">Aldec</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a></div></p> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com1tag:blogger.com,1999:blog-7343793379868603098.post-36265057851984776082013-10-23T00:19:00.001-07:002013-10-23T00:19:01.275-07:00Catch-up with SVA 2009-2012 updates – free Webinar on Oct 31st<h4><a href="http://www.aldec.com/en/events/338" target="_blank">Simplified Assertion Adoption with SystemVerilog 2012 (EU/ASIA)</a></h4> <p><em>Date: Thursday, October 31st, 2013</em></p> <p><em>Time: 2:00 PM-3:00 PM IST – India time / 9:30 AM-10:30 AM CET (European time)</em><em>        </em></p> <p><em>Host:</em> <strong><u>Aldec,</u> </strong>CVC’s valued EDA partner (<a href="http://www.aldec.com" target="_blank">www.aldec.com</a>) <br /><em>Presented by: Srinivasan Venkataramanan (<a title="http://www.linkedin.com/in/svenka3" href="http://www.linkedin.com/in/svenka3" target="_blank">http://www.linkedin.com/in/svenka3</a>)</em></p> <p><em>                       </em>CVC (Contemporary Verification Consultants <a href="http://www.cvcblr.com" target="_blank">www.cvcblr.com</a>) – Aldec’s Training Partner, </p> <p>Assertions have been in use for over a decade for now, however, writing detailed, temporal expressions in plain SystemVerilog (SV) 2005 has been at times a demanding task for first time users. While it gets easier as users mature with SVA, the language has made it more straightforward to express complex temporals with recent additions to the standard.</p> <p>With SV 2012 LRM becoming freely available to all users, the adoption is expected to grow much faster. This webinar will demonstrate some of the important LTL operators added to the SVA such as until, eventually, etc. Using real-life case studies, the presenter demonstrates how these new operators can significantly reduce complexity of SVA coding. Attendees will be taken through a small, real-life protocol and shown how to break down the requirements in an “edge-by-edge” approach to coding SVA. An Ethernet-like protocol case study will be used to demonstrate the value of assertions while building driver BFMs in UVM. This clearly highlights the benefit of adding assertions upfront in a project cycle by helping reduce the TB development time.</p> <p>This is a FREE webinar, but registration is required. Choose your slot depending on your geography.</p> <p>India/Asia/Europe: <a title="http://www.aldec.com/en/events/338" href="http://www.aldec.com/en/events/338" target="_blank">http://www.aldec.com/en/events/338</a></p> <p>USA/Rest Of the World: <a href="http://www.aldec.com/en/events/339" target="_blank">http://www.aldec.com/en/events/339</a></p> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-31746716152925216792013-04-21T14:33:00.001-07:002013-04-21T14:33:02.011-07:00Mind the GAP – even in SystemVerilog macro definition<p>SystemVerilog enhances the TEXT-MACRO feature (a.k.a `define-s by many young engineers) of Verilog by a good length. Significant enhancements done are:</p> <ol> <li>Added capability to extend the definition to multiple lines </li> <li>Added macros with arguments; </li> <li>Macro arguments can have default values too! (not fully supported by all tools though) </li> </ol> <p>However there are few caveats – in general any text-macro usage in any computer language is hard to debug when it fails to compile. So be ready to be patient while debugging macro code. </p> <p>Recently an online forum user asked a question on SystemVerilog macros. Here is what the user defined to start with:</p> <p><a href="http://lh4.ggpht.com/-VCFuzn5m2PE/UXRbBzKAuKI/AAAAAAAAA48/AKMx7vn529k/s1600-h/image%25255B9%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh5.ggpht.com/-rs5xFXwKFiM/UXRbCY7vx1I/AAAAAAAAA5E/doVHAbDHFzI/image_thumb%25255B11%25255D.png?imgmax=800" width="294" height="91" /></a> </p> <p>To a bare eye, the above looks fine. However a  SV compiler would through an error at it. As per the LRM:</p> <p> </p> <blockquote> <p><font size="3">If formal arguments are used, the list of formal argument names shall be enclosed in parentheses following <br />the name of the macro. The left parenthesis shall follow the text <strong><u>macro name immediately, with no space in <br />between.</u></strong></font></p> </blockquote> <p>In other words – as it is with any Metro station sign, you should be careful with the GAP/spaces :-) </p> <p><img src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjh5UDyhKfl8rsRqPW6nyz0Nt0GaO0NzzvCcBc3VzkO9tm8Pc6pBdyZSqglTrHgXW-Fs5XIVlxkH2LpFmNr_6aB6MzANOHZVMt46RXFYDypzXb7D36W_45uR7gwQLnyYomErPn1zK_Mtd0/s1600/mind_the_gap-logo.jpg" width="308" height="205" /></p> <p><a href="http://lh5.ggpht.com/-sCzUORFPDV0/UXRbCir64sI/AAAAAAAAA5M/kq1s62nkP-I/s1600-h/image%25255B12%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh3.ggpht.com/-wtXGmaMn3Js/UXRbDPnG-AI/AAAAAAAAA5U/Gg_3yOpAoZw/image_thumb%25255B27%25255D.png?imgmax=800" width="246" height="88" /></a> </p> <p>Notice that “extra space” after the macro name <strong><em>CHECK1</em></strong> is now gone! This works in Questa 10.2.</p> <p>So next time when you code your macros – mind the GAP :-)</p> <p><a href="http://www.cvcblr.com" target="_blank">TeamCVC</a></p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:082be9b5-0d3c-4ab7-82c7-fa7db9968c60" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SystemVerilog" rel="tag">SystemVerilog</a>,<a href="http://technorati.com/tags/Verilog" rel="tag">Verilog</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-73942201205937599152013-04-19T09:27:00.001-07:002013-04-19T09:27:38.241-07:00Smart constraint modeling in SystemVerilog<p>With SystemVerilog language gaining popularity among user, it is getting interesting to see user asking similar/repeating “patterns” of challenges in various forums. One of them is on constraint modeling when it becomes more than simple “a > 10” like stuff. Recently a VerifAcademy user asked:</p> <p> </p> <blockquote> <p>in my testbench i have to make a random signal "[31:0] distortion". it must contain one (or, in other case, two) hot bit(s) (hot bit is "1", all others are "0"). So i have a problem with writing a constraint: i really don't want to write all possible combinations of these bits (if there are two of them, there will be 32! combinations, so...). Does anyone have solution for this problem?</p> </blockquote> <p> </p> <p>A smart model is indeed available via 2 features of this vast language – System Verilog:</p> <p>1. A handy system function to count the number of “ones”</p> <p>2. Constraints can use functions in expressions. </p> <p>Combining the above two, here is a full solution to the above problem along with a sample run from Questa 10.2</p> <p> </p> <p><a href="http://lh5.ggpht.com/-OkC3s2_8USk/UXFwdNMrQ_I/AAAAAAAAA4k/XcGyMoaa-oo/s1600-h/image%25255B21%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="image" border="0" alt="image" src="http://lh6.ggpht.com/-c2ygmSR4LRA/UXFweDfgrPI/AAAAAAAAA4s/AJTar36EFrg/image_thumb%25255B25%25255D.png?imgmax=800" width="639" height="407" /></a> </p> <p>Hope you enjoy the concise solution. Do call us via +91-9620209226 or <a href="mailto:training@cvcblr.com">training@cvcblr.com</a> for learning more about this wonderful language and its applicability for your verification projects.</p> <p><a href="http://www.cvcblr.com" target="_blank">TeamCVC</a></p> <p> </p> <p> </p> <p></p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:84cdb619-1468-42a0-a824-6c4923779065" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/systemVerilog" rel="tag">systemVerilog</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-31818940931588098252013-04-01T10:09:00.001-07:002013-04-01T10:09:07.041-07:00SystemVerilog 2009 macro `__FILE__ – absolute or relative path?<p>As many of our customer learn during our regular <a href="http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf" target="_blank"></a><a href="http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf" target="_blank">VSV training sessions</a>,</a> System Verilog added `__FILE__ & `__LINE__ macros similar to C language. It is quite handy for debugging remotely developed code for a newcomer especially. Recently at an UVM forum a user asked how to get the relative path vs. absolute path from this macro. Consider the following code:</p> <p><a href="http://lh6.ggpht.com/-um6DhiTzIgY/UVm_D0g9sCI/AAAAAAAAA3c/_WZO5Q1Gr8Y/s1600-h/image%25255B4%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh3.ggpht.com/-fz-oAf3dw-A/UVm_Evszf7I/AAAAAAAAA3k/v3sObplC7p0/image_thumb%25255B6%25255D.png?imgmax=800" width="462" height="250" /></a> </p> <p> </p> <p>The SV LRM says;</p> <blockquote> <p><strong><u>22.13 `__FILE__ and `__LINE__</u></strong> <br />`__FILE__ expands to the name of the current input file, in the form of a string literal. This is the path by <br />which a tool opened the file, </p> </blockquote> <p>So if you provide the absolute path name during compile command, you are bound to get the FULL PATH.</p> <p>Questa when run with full path to the file as below:</p> <p><a href="http://lh3.ggpht.com/-98Qj0ISjFJQ/UVm_FDwVTTI/AAAAAAAAA3s/w0UcKss0FeE/s1600-h/image%25255B16%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh6.ggpht.com/-HScKJ6HCyKY/UVm_KzcB8lI/AAAAAAAAA30/0LFK132GgBc/image_thumb%25255B23%25255D.png?imgmax=800" width="558" height="78" /></a> </p> <p>produces the following output:</p> <p><a href="http://lh3.ggpht.com/-ZOVFleFJZtI/UVm_LGBVieI/AAAAAAAAA38/IJfSjlFDJFs/s1600-h/image%25255B10%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh5.ggpht.com/-Cl-17DrtC18/UVm_LrWFasI/AAAAAAAAA4E/taUonR3A3u4/image_thumb%25255B15%25255D.png?imgmax=800" width="600" height="93" /></a> </p> <p></p> <p></p> <p> </p> <p>And you could get a pretty short output as below if you do a “magic” (Left as exercise to the interested reader :-) )</p> <p><a href="http://lh4.ggpht.com/-nojhXl0dBWg/UVm_L8JzcHI/AAAAAAAAA4M/d91LwynK62c/s1600-h/image%25255B23%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh4.ggpht.com/-CRohvbHNw_Q/UVm_McU5VJI/AAAAAAAAA4U/LJeo3r-gt5c/image_thumb%25255B34%25255D.png?imgmax=800" width="422" height="74" /></a> </p> <p>Enjoy System Verilog and have fun!</p> <p><a href="http://www.cvcblr.com" target="_blank">TeamCVC</a> </p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:5c11255b-b589-496b-8a9a-7706b5eff072" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SystemVerilog" rel="tag">SystemVerilog</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com4tag:blogger.com,1999:blog-7343793379868603098.post-9754850491484143122013-03-22T10:47:00.001-07:002013-03-22T10:47:41.526-07:00SV solver puzzle part II – “guidance” vs. “dictation”<p> </p> <p>With one of our recent blog entries on SystemVerilog constraint solver (<a title="http://www.cvcblr.com/blog/?p=725" href="http://www.cvcblr.com/blog/?p=725" target="_blank">http://www.cvcblr.com/blog/?p=725</a>) becoming so popular, several readers have contacted us via email to know little more about the puzzle. Specifically they wanted to understand how the solver ordering of variables is determined. Consider the same example as in that previous blog entry:</p> <p><img title="cnst2" border="0" alt="cnst2" src="http://www.cvcblr.com/blog/wp-content/uploads/2013/03/cnst2_thumb.png" width="465" height="207" /></p> <p>As noted in the previous blog, this creates an “implicit ordering” of variables – i.e. ‘v1” is solved BEFORE “v2”. A smart engineer (<a href="http://www.linkedin.com/pub/muthurasu-sivaramakrishnan/15/38/77b/" target="_blank">Muthurasu Sivaramakrishnan</a>) asked this: </p> <ul> <li><em>Nice one. However, why cant we use Solve.. Before constraint in this scenario? </em></li> </ul> <p>The answer is a little involved with yet-another subtlety in the language, and hence this new entry:</p> <p>This reader’s question boils down to whether the above constraint “<strong><em>cst_ordered”</em></strong> is same as the following;</p> <blockquote> <p><strong><em>constraint cst_guidance {solve v1 before v2;}</em></strong></p> </blockquote> <p>First intuition says YES, but the answer unfortunately is NO. In SV there are 2 kinds of solver ordering - an ordering constraint is more of a "guidance on probability" and does NOT change the solution space. Hence it can't lead to a failure from a success or vice-versa. This is what happens with a <strong><em>solve..before – </em></strong>i.e. it is simply a “guidance” or suggestion to the solver.</p> <p>However the ordering that gets enforced via function call is more <strong>STRICT/DICTATIVE</strong> in nature. It enforces the order by further "subdividing" the solution space and in a sense invokes the solver twice. In Questa you can actually see this in action via -solveverbose - you will see 2 "Working Set" prints for function based constraint:</p> <p>1. First the solver gets “dictated” to solve “v1” INDEPENDENTLY. In a random choice, say it picked a value “1”</p> <p>2. Now the solver takes up the next variable to be solved in THAT order, i.e. “v2” – you see in Questa the “Working Set’ print with details (note: <strong><em>randomize</em></strong> is called only once per iteration in user code)</p> <p><a href="http://lh5.ggpht.com/-TX0Wp7TgfqI/UUyZN625eaI/AAAAAAAAA3E/XbZqWTEnqF0/s1600-h/cnst4%25255B6%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="cnst4" border="0" alt="cnst4" src="http://lh5.ggpht.com/-fwu5U5fta7M/UUyZO5RZsLI/AAAAAAAAA3M/l2wkIUGTl58/cnst4_thumb%25255B4%25255D.png?imgmax=800" width="707" height="456" /></a> </p> <p> </p> <p>So this leads to a constraint solver failure. Whereas a mere “guidance” shown by a <strong><em>solve..before</em></strong> would have solved both the variables TOGETHER, leading to a successful solving operation.</p> <p>Bottomline: The function call “strictly enforces” the solve order, while the “<strong><em>solve..before”</em></strong> is more of a “guidance/suggestion”.</p> <p>To learn more about this and other advanced SystemVerilog topics, join our training via <a href="http://www.cvcblr.com/trainings">www.cvcblr.com/trainings</a> </p> <p>Good Luck</p> <p><a href="http://www.cvcblr.com" target="_blank">TeamCVC</a> </p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:8044b162-cc6e-4180-bf69-14cc3ea6a725" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SystemVerilog" rel="tag">SystemVerilog</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a>,<a href="http://technorati.com/tags/Constraints" rel="tag">Constraints</a>,<a href="http://technorati.com/tags/Questa" rel="tag">Questa</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-40172936428323418892013-03-21T12:13:00.001-07:002013-03-21T12:13:33.269-07:00SVA: default disable – a boon or a bane?<p>As the SVA usage expands/grows in the industry, so do the language syntax/features. One of the recent (2009) addition to System Verilog language was the ability to code “default disabling condition”.</p> <p>It is very handy to have an “inferred” disabling condition for all assertions so that one can save on verbosity while typing – every assertion doesn’t have to repeat;</p> <blockquote> <p>  a_without_default_disable : assert property (disable iff (!rst_n) my_prop);</p> <p>vs. </p> <p>a_with_default_disable : assert property (my_prop);</p> </blockquote> <p>Obviously anything that helps to save some typing is a BOON.<img src="http://t3.gstatic.com/images?q=tbn:ANd9GcTGeSzFySeqa9bE-SCQ2d1TKVk5aTcdS7zaJaZbXcTMIO7cm5akLQ" width="87" height="76" /></p> <p>However there are some special category of assertions that may get unintentionally disabled by this. For instance the “reset-checks” – assertions that check the reset value of various DUT outputs. For e.g. </p> <ul> <li>FIFO empty flag during reset </li> <li>serialout signal from a de-serializer design </li> </ul> <p>We recently had a similar DUT being verified with SVA. In the below code, notice the “default disable” and the reset-check</p> <p><a href="http://lh6.ggpht.com/-3jBAQYjgki4/UUtbzvEwx5I/AAAAAAAAA2M/XRP3exVauog/s1600-h/sva_def_dis_1%25255B3%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="sva_def_dis_1" border="0" alt="sva_def_dis_1" src="http://lh6.ggpht.com/-hrew_E16Zlo/UUtb0vto8yI/AAAAAAAAA2U/_xMKj2QloIQ/sva_def_dis_1_thumb%25255B1%25255D.png?imgmax=800" width="612" height="447" /></a> </p> <p>As the callout/marking shows – there is a bug in DUT, the signal “serialout” is indeed HIGH during reset, yet the assertion doesn’t fire (Questa shows it as INACTIVE – meaning it is a vacuous success in this case). </p> <p>So that begs the question of “is the default disable a boon or a BANE”?        <img src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjhkhjO3QAAS2fQFCpVXmEF4ln7429w1gN6uV-IhCab3uKJ1ZoyQXj97lEGcrZwYhyNyogD_2JiHTlnZ34wSlBBcBgz-a4gyT0HlgDXWHkWIi-U6VEWx-NK8AZZdbqaCzhmJ09Gq-MzzJY/s1600/Boon-Bane-714094.jpg" width="209" height="119" /></p> <p>The answer is – you need a methodology and a plan while doing your assertions – categorize the assertions appropriately. Specifically group them as:</p> <ul> <li>Reset checks </li> <li>Functional checks </li> <li>Low Power checks </li> </ul> <p>etc. Here is a nice work-around for this:</p> <ul> <li>Use an explicit “<strong><em>disable iff (1’b0)”</em></strong> for those special category assertions </li> </ul> <a href="http://lh5.ggpht.com/-C3mFDKUk0q0/UUtb1EKJNzI/AAAAAAAAA2c/jxzwt_At2rY/s1600-h/sva_def_dis_2%25255B5%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="sva_def_dis_2" border="0" alt="sva_def_dis_2" src="http://lh3.ggpht.com/-MNxDgDviUCg/UUtb1liBG-I/AAAAAAAAA2k/d4Onv9GZ1Z8/sva_def_dis_2_thumb%25255B3%25255D.png?imgmax=800" width="587" height="223" /></a> <p> </p> <p>Now Questa flags it nicely as below:</p> <p><a href="http://lh3.ggpht.com/-8Q2ESRAOO0Q/UUtb2URmMyI/AAAAAAAAA2s/3Zcdp9sL8yU/s1600-h/sva_def_dis_3%25255B4%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="sva_def_dis_3" border="0" alt="sva_def_dis_3" src="http://lh5.ggpht.com/-eKBWi5N9jQE/UUtb3DYhPdI/AAAAAAAAA20/CNPq8m-4-0w/sva_def_dis_3_thumb%25255B2%25255D.png?imgmax=800" width="593" height="223" /></a> </p> <p>So do use the new SVA stuff on “<strong><em>default disable”</em></strong> – it is indeed a BOON. Just make sure you “think” before you code those special category of assertions.</p> <p>This is part of our larger story of ABV methodology being rolled out as next generation verification training sessions at <a href="http://www.cvcblr.com" target="_blank">CVC</a>. So do contact us via <a href="mailto:training@cvcblr.com">training@cvcblr.com</a>  for more advanced, practical usage of this wonderful technology.</p> <p>Good Luck</p> <p><a href="http://www.cvcblr.com" target="_blank">TeamCVC</a></p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:0aacfb85-d055-43db-b69f-1eb9b22ce823" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SystemVerilog" rel="tag">SystemVerilog</a>,<a href="http://technorati.com/tags/SVA" rel="tag">SVA</a>,<a href="http://technorati.com/tags/ABV" rel="tag">ABV</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com1tag:blogger.com,1999:blog-7343793379868603098.post-60427838821707985082013-03-13T09:03:00.001-07:002013-03-13T09:03:02.100-07:00SystemVerilog constraint puzzle – treat for CRV lovers<p> Are you an avid fan of CRV – Constraint Random Verification? Have you played enough with System Verilog constraints? Many of our customers having attended our regular <a href="http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf" target="_blank">VSV training</a> (<a title="http://www.cvcblr.com/trainings" href="http://www.cvcblr.com/trainings">http://www.cvcblr.com/trainings</a>) do become so! One of the nice features of SystemVerilog constraint mechanism is its “bi-directionality” – a key feature that makes the distribution fairly wide spread and makes the state space well covered. </p> <p>The industry has learnt it over the last decade of CRV usage – bidirectional constraints are better than unidirectional ones (that was the default in previous generation solver inside popular tool like Specman – called PGen. Even Specman has moved to a more robust, bi-directional IGEN/Intelligen few years back).</p> <p>In SV this bi-directionality is subtle. Consider the code below:</p> <p></p> <p><a href="http://lh5.ggpht.com/-bXZC9bgev6A/UUCjKZt3q_I/AAAAAAAAA1k/v9tA_3RAx94/s1600-h/cnst2%25255B5%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="cnst2" border="0" alt="cnst2" src="http://lh3.ggpht.com/-5aB1IcwTUUM/UUCjLIgWE1I/AAAAAAAAA1s/U8-73mDhE4k/cnst2_thumb%25255B3%25255D.png?imgmax=800" width="465" height="207" /></a> </p> <p>To an average SV engineer the above 2 constraints look “same” as the function is trivially doing a return job. However they are different for an avid SV user or a solid SV solver such as Questa from Mentor. As per LRM:</p> <blockquote> <p><strong>Random variables used as function arguments shall establish an implicit variable ordering.</strong></p> </blockquote> <p>Hence in case of “<strong><em>cst_ordered”</em></strong>, the variable “v1” is solved FIRST and then the “v2” – i.e. they are solved separately and not together (Which is what happens with ‘<strong><em>cst_bidir”</em></strong>). </p> <p>So what’s the big deal? Consider “v1” is chosen to be “1” first, then the solver has NO solution for “v2” :-( leading to a constraint failure.</p> <p>So, next time when you use a function in a constraint, remember/recall/read this blog :-)</p> <p>Care for a proof? See what Questa’s solveverbose prints:</p> <blockquote> <p>qverilog file.sv –R –solveverbose=2</p> </blockquote> <p><a href="http://lh5.ggpht.com/-D-88sYMto0I/UUCjLy21ixI/AAAAAAAAA10/ZiotjOROoYc/s1600-h/cnst3%25255B4%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="cnst3" border="0" alt="cnst3" src="http://lh5.ggpht.com/-CGf9nwhI0Sg/UUCjNPdUcsI/AAAAAAAAA18/7IMazdOQYZk/cnst3_thumb%25255B2%25255D.png?imgmax=800" width="704" height="520" /></a> </p> <p>Enjoy CRV, enjoy SystemVerilog. In case you want to delve deeper into SV, do call us via <a href="mailto:training@cvcblr.com">training@cvcblr.com</a> </p> <p><a href="http://www.cvcblr.com" target="_blank">TeamCVC</a></p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:91249610-b17b-43ff-837e-7e6ced3daa9e" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SystemVerilog" rel="tag">SystemVerilog</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a>,<a href="http://technorati.com/tags/Questa" rel="tag">Questa</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-56459844681658500212013-02-19T10:19:00.001-08:002013-02-19T10:19:08.611-08:00Dare to think beyond UVM for SoC verification<h3> </h3> <p>Over the past few years, the term “pre-silicon verification” has been quite popular and several technology advancements have helped in solving that puzzle. Some of the biggest contributors have been languages such as <b><i>e</i></b>/Specman and SystemVerilog with supporting technologies such as constrained-random verification (CRV), coverage-driven verification (CDV) and assertion-based verification (ABV). All these three technologies when used in unison addressed the challenge at the block or intellectual property (IP)level fairly well. Recently UVM has been developed as a framework to use these languages in the best possible manner to try and keep these technologies scalable to larger designs, such as system-on-chips (SoC). Thanks to the Accellera committee devoting time and effort, UVM is becoming quite popular and the de-facto IP verification approach.</p> <p>However with SoCs, there are several new challenges in the verification space that threaten to quickly outgrow the current prevalent technologies such as CRV and UVM. One of the key pieces in an SoC is the embedded processor/CPU – either single or multiple of them. Witha transaction-based verification approach such as UVM, typically the CPU gets modeled as a BFM (bus functional model). Some customers term this as a “headless environment” indicating that the “head” of a SoC is indeed the CPU(s). In theory, both the CPU bus and the peripherals can be made to go through grinding transactions via their BFMs.</p> <p>                                       <a href="http://lh5.ggpht.com/-nMxPEAnj22Q/USPB7nl7jcI/AAAAAAAAAzw/0ygXzM5vzEI/s1600-h/image%25255B3%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh3.ggpht.com/-rc6Cx2zN__M/USPB8uYZoII/AAAAAAAAAz4/ZYsHZTZvsbk/image_thumb%25255B1%25255D.png?imgmax=800" width="471" height="411" /></a> </p> <p align="center">                                                          Figure-1: Sample headless SoC environment</p> <p>While this certainly helps to get started, soon engineers find it difficult to scale things up with advanced UVM features such as the Virtual Sequencer, Virtual Sequences etc. Even with deep understanding of these, developing scenarios around them has not been an easy task. The length of such sequences/tests, their debug-ability and review-ability have started begging the question of “are we hitting the limits of UVM” - especially in the context of SoCs?</p> <p>If you thought this is too premature of an assessment, hold-on: the trouble has just started. Anyone involved in an SoC design cycle would agree that the so called “headless environment” is just a start, and would most certainly want to run with the actual CPU RTL model(s) running C/assembly code running on the same.</p> <p>                                             <a href="http://lh4.ggpht.com/-dRPKIMpXXE8/USPB9Vl7teI/AAAAAAAAA0A/4AMM8vhgmHw/s1600-h/image%25255B8%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh4.ggpht.com/-mpkqkvRKrTI/USPCDSYrSZI/AAAAAAAAA0I/TXIxYbFhuHM/image_thumb%25255B4%25255D.png?imgmax=800" width="350" height="485" /></a> </p> <p>                              Figure-2: SoC environment with actual CPU RTL running C/assembly code</p> <p>This is a significant step in the pre-silicon verification process. The current UVM focus doesn’t really address this immediate need, thereby forcing users to create a separate flow with a C-based environment around the CPU and hand-coding many of the same scenarios that were earlier tested with “headless UVM” environment. Though the peripherals can still reuse their UVM BFMs, the “head” is now replaced with actual RTL and the co-ordination/synchronization among the peripherals needs to be managed manually – no less than a herculean task. We have heard customer saying “I’ve spent two months in re-creating concurrent traffic, a la the headless environment in the C-based setup”. </p> <p>The hunt has been on for a higher level modeling of the system level scenarios that can then be run on either a headless or C-based environment – keeping much of the scenarios as-is. Here is where the graphs start to make lot of sense as human beings are well versed with the idea of mind maps (<a href="http://en.wikipedia.org/wiki/Mind_map">http://en.wikipedia.org/wiki/Mind_map</a>) as a natural, intuitive way of thinking about simultaneous activities, interactions and flow of thoughts. </p> <p>Breker has been the pioneer in this space by introducing a graph-based approach to functional verification. With graphs, users capture the IP level scenarios as nodes and arcs making it ideal to capture the typical day-in-the-life (DITL) for the IP. Many such IP-level graphs can then be quickly combined to form a SoC level scenario model such as the one below:</p> <p>                                                      <a href="http://lh4.ggpht.com/-9u1Z2qSev1k/USPCEfFXU1I/AAAAAAAAA0Q/kHWOTReMh08/s1600-h/image%25255B12%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh3.ggpht.com/-74Qe2scJeWw/USPCFCHPdxI/AAAAAAAAA0Y/bxDBIO6WAxM/image_thumb%25255B6%25255D.png?imgmax=800" width="380" height="315" /></a> </p> <p>                                                                           Figure-3: SoC level scenario model</p> <p>With a graphical scenario model, TrekSoc (<a href="http://www.brekersystems.com/products/treksoc">http://www.brekersystems.com/products/treksoc</a>), the flagship SoC verification solution from Breker, can then be asked to either churn out transactions for a headless environment or embedded C-tests for the actual CPU based system with a flip of a switch. </p> <p>                                 <a href="http://lh6.ggpht.com/-wZlJeo-bRiw/USPCF9VjTcI/AAAAAAAAA0g/PUXc7aoRRdc/s1600-h/image%25255B16%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh5.ggpht.com/-NN9PZGC5bdg/USPCG7n2XvI/AAAAAAAAA0o/S_0TwEL0QeM/image_thumb%25255B8%25255D.png?imgmax=800" width="566" height="346" /></a>    </p> <p>                                               Figure-4: Using scenario models with TrekSoC</p> <p>This is clearly way beyond current UVM intended goals as UVM is created to solve the problem of VIP reuse and it serves its purpose very well. </p> <p>Now, with C-tests being auto-generated, the possibilities are endless – they can be reused across the breadth of verification and validation in various platforms starting with simulation, through emulation/prototyping, and all the way up to post-silicon validation.</p> <p>Bottom line: UVM is serving the very purpose it has been developed for – to create interoperable, reusable VIPs. However a full SoC verification is much more than a bunch of VIPs. It requires next abstraction level models such as the graph based scenario models. Such scenario models can then be compiled by TrekSoC to produce C-tests and/or UVM transactions. </p> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-12079394886651547632013-02-19T07:56:00.001-08:002013-02-19T07:56:36.335-08:00Missed a UVM field macro? Be ready for surprises – and a debug assistant!<p>Recently a UVM user pondered over the following question:</p> <blockquote> <h4>randomization NOT happening for seq_item variable if uvm_field_* is NOT enabled?</h4> <p>(<a title="http://goo.gl/TNSaz" href="http://goo.gl/TNSaz" target="_blank">http://goo.gl/TNSaz</a>)</p> </blockquote> <p>To appreciate the issue, consider the code snippet as below:</p> <p><a href="http://lh4.ggpht.com/-uAZ3HXVK_z0/USOglqLuJ5I/AAAAAAAAAxs/C-rVUDzwGp0/s1600-h/uvm_dbg_1%25255B3%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="uvm_dbg_1" border="0" alt="uvm_dbg_1" src="http://lh5.ggpht.com/-N056nihm1cE/USOgmTeEiDI/AAAAAAAAAx0/0vfKKTj6TOA/uvm_dbg_1_thumb%25255B1%25255D.png?imgmax=800" width="487" height="215" /></a> </p> <p>Since both <strong><em>hdr </em></strong>and <strong><em>pkt_len </em></strong>are declared rand, one expects them to be randomized. Note that one of the <strong><em>`uvm_field_int </em></strong>is commented – to demo the issue.</p> <p>Now a recipient/consumer of this transaction does a <strong><em>copy/clone</em></strong> at destination. See a code snippet:</p> <p><a href="http://lh5.ggpht.com/-SWCaig2hjTM/USOgnKc5fiI/AAAAAAAAAx8/4ppf0SCjA7g/s1600-h/uvm_dbg_3%25255B3%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="uvm_dbg_3" border="0" alt="uvm_dbg_3" src="http://lh3.ggpht.com/--DGzOEEkNvY/USOgnwBMVfI/AAAAAAAAAyE/L40jYgeDtgc/uvm_dbg_3_thumb%25255B1%25255D.png?imgmax=800" width="511" height="219" /></a> </p> <p></p> <p>So far so good, let’s see what happens in a typical Questa simulation:</p> <p><a href="http://lh6.ggpht.com/-D1FR9yJ4mxI/USOgovrIymI/AAAAAAAAAyM/qNDEq4QShDc/s1600-h/uvm_dbg_4%25255B5%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="uvm_dbg_4" border="0" alt="uvm_dbg_4" src="http://lh3.ggpht.com/-1SJlc2w3RuE/USOgpgYRo6I/AAAAAAAAAyU/YcySVm3hFcg/uvm_dbg_4_thumb%25255B3%25255D.png?imgmax=800" width="577" height="132" /></a></p> <p> The above results of <strong><em>hdr </em></strong>being NOT generated occurs consistently for all seeds (See the forum post if needed). So a typical user suspects that the missing <strong><em>uvm_field_int</em></strong> macro does control the randomization – though not intuitive/true. This could consume quite a few debug cycles (recall that the macro above is commented for demo only, in actual work, as reported in that forum posting, user forgot to  add that at the first place).</p> <h2><u>A Debug assistant</u></h2> <p>Now as in our regular <a href="http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf" target="_blank">VSV training sessions</a> (<a href="http://www.cvcblr.com/trainings" target="_blank">www.cvcblr.com/trainings</a>) , we showcase the potential applications of <strong><em>post_randomize</em></strong> and one of the prominent ones is to “debug” the generated fields. See below code snippet:</p> <p><a href="http://lh4.ggpht.com/-xwXnLEGyYcw/USOgqYZjB6I/AAAAAAAAAyc/yPVFNDBmLSo/s1600-h/uvm_dbg_5%25255B3%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="uvm_dbg_5" border="0" alt="uvm_dbg_5" src="http://lh6.ggpht.com/-IO3qsT6VFtM/USOgrEYitbI/AAAAAAAAAyk/bKbyskshTTo/uvm_dbg_5_thumb%25255B1%25255D.png?imgmax=800" width="591" height="288" /></a> </p> <p>With the above code added, here is what our friendly Questa has to show for us in simulation:</p> <p><a href="http://lh3.ggpht.com/-tVfxy_ztdoo/USOgr8OYP1I/AAAAAAAAAys/W2K8dQMWI30/s1600-h/uvm_dbg_2%25255B3%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="uvm_dbg_2" border="0" alt="uvm_dbg_2" src="http://lh6.ggpht.com/-0c-eFt1W19w/USOgsrkgYOI/AAAAAAAAAy0/ZWjEcqwGSaM/uvm_dbg_2_thumb%25255B1%25255D.png?imgmax=800" width="550" height="172" /></a> </p> <p>So clearly the <strong><em>hdr </em></strong>field does get randomly generated. It is only when a copy of the container class being created, it skips the “copy process”. And this has to do with the lack of macro. Focus on the missing/commented macro below:</p> <p> <p></p> <p><a href="http://lh4.ggpht.com/-uAZ3HXVK_z0/USOglqLuJ5I/AAAAAAAAAxs/C-rVUDzwGp0/s1600-h/uvm_dbg_1%25255B3%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="uvm_dbg_1" border="0" alt="uvm_dbg_1" src="http://lh5.ggpht.com/-N056nihm1cE/USOgmTeEiDI/AAAAAAAAAx0/0vfKKTj6TOA/uvm_dbg_1_thumb%25255B1%25255D.png?imgmax=800" width="487" height="215" /></a> </p> <p>Hope the above makes it self-explanatory – add the macro, you get <strong><em>copy/clone</em></strong> enabled for that specific field. So 2 lessons learnt today:</p> <p>1. Use field macros consistently</p> <p>2. More importantly, use <strong><em>post_randomize</em></strong> as your friendly, automated debug assistant for random generation!</p></p> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-56119817734351438862013-02-09T12:10:00.001-08:002013-02-09T12:10:08.349-08:00Simple assertion can save hours of debug time<p>Recently a user sought to assign a 4-state array (declared as <strong><em>logic</em></strong>) from the DUT side to a 2-state, <strong><em>bit</em></strong> typed array on TB side. Quite normal and intelligent choice of datatype – as all the TB components at higher level should work on abstract models. However there are 2 important notes – one on the “syntax/semantic” and other on real functional aspect. </p> <p>Focusing on the functional aspect first (as the semantic would be caught by the compiler anyway), what if the DUT signal contained X/Z on the 4-state array value? </p> <p> </p> <p><a href="http://lh5.ggpht.com/-7aKrgDr0_Lg/URatDc2hpvI/AAAAAAAAAwM/yiNTecPfM-4/s1600-h/Picture2%25255B4%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="svd1" border="0" alt="svd1" src="http://lh5.ggpht.com/-HpIotDBurh0/URatEKjSd2I/AAAAAAAAAwU/7uJirrh08Pg/svd1%25255B4%25255D.png?imgmax=800" width="655" height="221" />  </a></p> <p> </p> <p>When you assign it to the 2-state array counterpart on the TB side – there is information loss and potentially wrong data :-(</p> <p> </p> <p><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="svd2" border="0" alt="svd2" src="http://lh3.ggpht.com/-2accyXEoBsY/URatFJykO6I/AAAAAAAAAwc/JYJWEK1sHoM/svd2%25255B3%25255D.png?imgmax=800" width="738" height="178" /></p> <p>Here is where a simple assertion could save hours of debug time for you. Recall that SV has a handy system-function to detect unknown values. One could write a simple assertion using that function at the DUT-TB boundary. See the full code below, with the assertion part highlighted:</p> <p> <a href="http://lh4.ggpht.com/-CGuDz7wzbrE/URatF08mkWI/AAAAAAAAAwk/C85E8UUY_Sk/s1600-h/SVD_SVA%25255B5%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="SVD_SVA" border="0" alt="SVD_SVA" src="http://lh6.ggpht.com/-AEQPrQx-HMo/URatG69oq2I/AAAAAAAAAws/SZB_h_Z_ue8/SVD_SVA_thumb%25255B3%25255D.png?imgmax=800" width="688" height="399" /></a></p> <p>With the SVA included, here is a transcript – Thank GOD, I used assertions :-)</p> <p><a href="http://lh5.ggpht.com/-7aKrgDr0_Lg/URatDc2hpvI/AAAAAAAAAwM/yiNTecPfM-4/s1600-h/Picture2%25255B4%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="Picture2" border="0" alt="Picture2" src="http://lh3.ggpht.com/-T0Udi13AR6M/URatH63hXVI/AAAAAAAAAw0/Cp2_SYY8x7g/Picture2_thumb%25255B4%25255D.png?imgmax=800" width="658" height="347" /></a></p> <p>So next time you move data from DUT-2-TB, consider this simple trick.</p> <p>For those wondering what’s the compile time issue in dealing with 4-state vs. 2-state, read VerifAcademy forum @ <a title="http://bit.ly/11xsgO0" href="http://bit.ly/11xsgO0" target="_blank">http://bit.ly/11xsgO0</a></p> <p> <a href="http://www.cvcblr.com" target="_blank">TeamCVC</a></p> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-50906102584548832302013-02-09T10:25:00.001-08:002013-02-09T10:25:13.335-08:00Pragmatic choice of ABV language - PSL still shines better than SVA<p> </p> <p>As many of our readers would recall, <a href="http://www.cvcblr.com" target="_blank">CVC</a> first became very visible to the industry with our early contribution to the assertion-based verification (ABV) via IEEE-1850 PSL (Property Specification Language). Back in 2004 we co-authored our first book on this wonderful language, first of its kind in the temporal assertion languages to become a standard (<a title="https://www.facebook.com/cvcblr" href="https://www.facebook.com/cvcblr" target="_blank">See our timeline in Facebook for more</a>). Since then it has been a wonderful run of events in this world of functional verification for close to a decade by now. </p> <p>One of the significant features of PSL has been its simplicity and succinct means of expressing complex temporals through its “Foundation Language” (a.k.a LTL style) subset. We talk about this in detail in our PSL book (<a title="http://www.systemverilog.us/psl_info.html" href="http://www.systemverilog.us/psl_info.html" target="_blank">http://www.systemverilog.us/psl_info.html</a>). Recently a user came up with a nice requirement at Forum in Verification Academy (See: <a title="http://bit.ly/14JTHlI" href="http://bit.ly/14JTHlI" target="_blank">http://bit.ly/14JTHlI)</a></p> <p>The spec goes as follows:</p> <p><a href="http://lh3.ggpht.com/-7zCwsQ70NnQ/URaUdmOm00I/AAAAAAAAAus/f-YGv_Iqkos/s1600-h/PSL_in_SV_spec%25255B5%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="PSL_in_SV_spec" border="0" alt="PSL_in_SV_spec" src="http://lh3.ggpht.com/-GbmyiyXQTuU/URaUepguMyI/AAAAAAAAAu0/Ev9KIHBW93Y/PSL_in_SV_spec_thumb%25255B3%25255D.png?imgmax=800" width="687" height="213" /></a> </p> <p>The user attempted a simple SVA 2005 style, but got weird results, then our beloved co-author and guru of assertions, Ben Cohen provided assistance as below (unverified):</p> <p><a href="http://lh5.ggpht.com/-cSCP69M_D5w/URaUfbsRIGI/AAAAAAAAAu8/oKlMk9FxToY/s1600-h/SVA05%25255B4%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="SVA05" border="0" alt="SVA05" src="http://lh6.ggpht.com/-i9r9a6_gGnk/URaUgNOHFHI/AAAAAAAAAvE/nrPtJ4ow7iE/SVA05_thumb%25255B2%25255D.png?imgmax=800" width="690" height="163" /></a> </p> <p>Do the same in PSL with FL/LTL style:</p> <p><a href="http://lh3.ggpht.com/-uco1xxn6ZDE/URaUg0EpGrI/AAAAAAAAAvM/dCGn0YdAAew/s1600-h/PSL_in_SV%25255B3%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="PSL_in_SV" border="0" alt="PSL_in_SV" src="http://lh5.ggpht.com/--eNfFN4HAFU/URaUh80fvDI/AAAAAAAAAvU/YC6kv4RZHb8/PSL_in_SV_thumb%25255B1%25255D.png?imgmax=800" width="673" height="182" /></a> </p> <p>Now relate the PSL code back to user spec/requirement:</p> <blockquote> <p>May be simple, but drives me crazy..</p> <p>"Req" -> "Gnt" -> "Rel"</p> <p><strong>When granted, assert if it is going to Idle state before releasing the</strong> lock.</p> </blockquote> <p>Won’t you agree that PSL with its FL/LTL style is lot closer to the spec than the erstwhile SVA-05 sequence based approach? </p> <p>There is light at the end of tunnel:</p> <p>1. PSL works well, nice and is usable in all flavors – Verilog, SV, VHDL, SystemC etc.</p> <p>2. It costs nothing extra in tools – if you have paid for SV, it is very likely you got the PSL too </p> <p>3. SV 2009 standard did add this LTL features into it, but yet to be supported by many vendors. So your chances of using it in live projects is weak. Of-course push your vendor for it though.</p> <p>Bottomline – use what works today, PSL is alive & kicking and you’ve already paid for it in your tool. There is hardly any extra learning – if you know one temporal language, the syntax is very similar, so why not get pragmatic and use it!</p> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-83700007244592142902013-01-04T11:44:00.001-08:002013-01-04T11:44:22.753-08:00Is your UVM simulation hanging? Need a debug help? Use display_objections()<p>  As we wrap up an excellent UVM training for a well informed audience for a local customer at the very beginning of 2013, here is a quick tip for those verification work-horses trying to debug various UVM phase related hangs in their simulations. To be honest, this was developed for another customer way back in the middle of 2012, but never got published, so we decided to do it in early 2013. This is part of our <a href="http://lh3.ggpht.com/-tXlXjtWHtoE/UOcw7biKp7I/AAAAAAAAAs8/-NNgkgfaNyU/s1600-h/Un_UVM_logo%25255B2%25255D.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="Un_UVM_logo" border="0" alt="Un_UVM_logo" src="http://lh5.ggpht.com/-B0tmMfKFUyk/UOcw8W4c4xI/AAAAAAAAAtA/w9Ub5ftri00/Un_UVM_logo_thumb.jpg?imgmax=800" width="244" height="24" /></a> product line where-in we line up various solutions around UVM. </p> <p>The scenario that several customers face is that they have bunch of raise & drop objections, but somehow there is a mismatch of the “raise-to-drop” – i.e. some of the raised objections remained and never got dropped! While UVM comes with few handy plusargs - +UVM_PHASE_TRACE, +UVM_OBJECTION_TRACE etc. these don’t always point you to exact problem, atleast fast-enough. Here is a smarter approach:</p> <p>The uvm_objection base class provides a very nice debug routine named <strong><em>display_objections()</em></strong>. One may want to stick the following piece of debug code to a test:</p> <p><a href="http://lh6.ggpht.com/-9vcQCnyUh2E/UOcw9oA4XWI/AAAAAAAAAtM/Y-Y5vc_ed-A/s1600-h/apb_uvm_ph_hang_dbg%25255B4%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="apb_uvm_ph_hang_dbg" border="0" alt="apb_uvm_ph_hang_dbg" src="http://lh4.ggpht.com/-hDC_Seti2sk/UOcw_KgUO-I/AAAAAAAAAtU/0PmjtQaPAVw/apb_uvm_ph_hang_dbg_thumb%25255B2%25255D.png?imgmax=800" width="738" height="329" /></a></p> <p> </p> <p>Fork the above task along with your regular main_phase’s logic. When we run this in Questa for instance, here is what we get:</p> <p><a href="http://lh4.ggpht.com/-u2pNOIDPNoY/UOcxAXlnDqI/AAAAAAAAAtc/7Iuu8KxVs2Y/s1600-h/apb_uvm_ph_hang_dbg1%25255B4%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="apb_uvm_ph_hang_dbg1" border="0" alt="apb_uvm_ph_hang_dbg1" src="http://lh6.ggpht.com/-ZpmOM2oJXOQ/UOcxB5EHsbI/AAAAAAAAAtk/lS0YnEv3bCA/apb_uvm_ph_hang_dbg1_thumb%25255B2%25255D.png?imgmax=800" width="343" height="274" /></a> </p> <p>So the above indicates there are 3 folks opposing it with clear pointers to who they are. Now run further till you get the hang state, you should see:</p> <p><a href="http://lh5.ggpht.com/-vBX9YAn8_5Y/UOcxDFnZqgI/AAAAAAAAAto/YUtfFy2tcI8/s1600-h/apb_uvm_ph_hang_dbg2%25255B5%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="apb_uvm_ph_hang_dbg2" border="0" alt="apb_uvm_ph_hang_dbg2" src="http://lh5.ggpht.com/-gAAX8j_EgdQ/UOcxE7iifQI/AAAAAAAAAt0/YIg83NEB2BU/apb_uvm_ph_hang_dbg2_thumb%25255B7%25255D.png?imgmax=800" width="345" height="263" /></a> </p> <p> </p> <p>The above transcript clearly indicates that the monitor is the culprit that has a raise objection that’s not dropped yet!</p> <p>Good Luck and have fun with your SystemVerilog and UVM debug. <a href="http://www.cvcblr.com/about_us" target="_blank">Contact us</a> via <a title="http://www.cvcblr.com/about_us" href="http://www.cvcblr.com/about_us">http://www.cvcblr.com/about_us</a> if your team need hands-on problem solving level case studies such as above along with regular <a href="http://www.cvcblr.com/trainings" target="_blank">VSV, UVM training</a> (<a title="http://www.cvcblr.com/trainings" href="http://www.cvcblr.com/trainings">http://www.cvcblr.com/trainings</a>).</p> <p><a href="http://www.cvcblr.com " target="_blank">TeamCVC</a></p> <p><a href="http://www.cvcblr.com/blog">www.cvcblr.com/blog</a> </p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:c832417a-d6b2-43fd-8ce5-98df7391a7ca" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SystemVerilog" rel="tag">SystemVerilog</a>,<a href="http://technorati.com/tags/UVM" rel="tag">UVM</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a>,<a href="http://technorati.com/tags/training" rel="tag">training</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-82577542423417633512012-12-27T11:27:00.001-08:002012-12-27T11:27:50.063-08:00I know SystemVerilog, why bother me with UVM?<p>If you are a verification engineer in ASIC/FPGA domain, chances are very little that you have not heard of SystemVerilog. For the last 6+ years it has been making positive impacts to design and verification teams across digital design space. </p> <p>Given this fact, this is no surprise there are several young engineers who jumped on to the bandwagon and picked up the language to a certain level. Many successful engineers in this part of the world have taken <a href="http://www.cvcblr.com" target="_blank">CVC</a>’s <a href="http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf" target="_blank">VSV course</a> as a wise step towards the same. </p> <p>However when it comes to the production use, plain System Verilog falls behind in certain key areas. Make no mistake, it is a powerful language and is becoming even more powerful with the upcoming 2012 update. See our blog for more on those updates: <a href="http://www.cvcblr.com/blog">www.cvcblr.com/blog</a> </p> <p>Many users ask us – why do I need UVM on top of SystemVerilog. While there are ample number of marketing material available on the net for free on this, here is a humble, technical attempt to challenge a solid DV engineer with decent SV skills. </p> <p>Consider a simple Deserializer design: call it S2P (Serial-2-Parallel converter). It captures the input serial stream from start-to-end and sends out as parallel data at its output every 8 clocks. A typical waveform would look as below:</p> <p><a href="http://lh4.ggpht.com/-I3XqfKrDH4k/UNyhIog1zFI/AAAAAAAAArs/Y7vkY6vmrxA/s1600-h/s2p1%25255B5%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="s2p1" border="0" alt="s2p1" src="http://lh3.ggpht.com/-RmaJITpTYxE/UNyhJ_rX4WI/AAAAAAAAArw/lyWmCohK9ys/s2p1_thumb%25255B3%25255D.png?imgmax=800" width="594" height="317" /></a> </p> <p>Now, let’s say that you are SV aware to the extent that you can comfortably create a verification environment in say 1 or 2 hours for this simple design.</p> <p>Now let’s try and do “verification” – add a negative test – i.e. create a scenario in which:</p> <ul> <li>There are <strong><em>ser_sop</em></strong> with NO <strong><em>ser_eop </em></strong>in between</li> </ul> <p>See a sample screenshot below:</p> <p><a href="http://lh5.ggpht.com/-oiqXeKXw890/UNyhLZpzqZI/AAAAAAAAAr8/qQPUzxTCEao/s1600-h/s2p2%25255B4%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="s2p2" border="0" alt="s2p2" src="http://lh6.ggpht.com/-_uk8ybY28II/UNyhM6DKfBI/AAAAAAAAAsA/FqYdczw9LiU/s2p2_thumb%25255B2%25255D.png?imgmax=800" width="589" height="252" /></a> </p> <p>Remember, it is a negative test and hence you are <strong>NOT allowed to change any existing code</strong>. Can you achieve this in plain SystemVerilog without UVM? </p> <p></p> <p>If the answer is simple YES, we would love to hear your solution (add via comments here, below). No, don’t think of tricks like “force/release” etc. Attempt it as a pure SystemVerilog coding exercise. </p> <p>The reality is – of-course we can, if we architect it upfront with factory and/or callback. That’s kind of what a framework such as UVM does for you. So UVM is nothing but 100% SystemVerilog, but wrapped in with a series of base-classes, built-in features that make your ‘verification” easy. </p> <p>Join us for our upcoming <a href="http://www.cvcblr.com/trainings" target="_blank">UVM training session</a> to know more on this challenge. </p> <p>Bottomline – UVM is made to make your verification task easier, though it achieves it through a myriad of base classes. Luckily, users need to bother with only about half-a-dozen of them or maybe 10. But that’s only if you are educated well on UVM and trained by experts. If not, chances are you will loose yourself in the UVM base-class maze trying to make a decent way-out! Choice is yours!</p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:41e0c107-8aac-4d35-a661-8f698f9805a8" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SystemVerilog" rel="tag">SystemVerilog</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a>,<a href="http://technorati.com/tags/UVM" rel="tag">UVM</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com2tag:blogger.com,1999:blog-7343793379868603098.post-29203904445069149182012-12-26T16:43:00.001-08:002012-12-26T16:43:07.230-08:00Did you miss multiple-inheritance in SystemVerilog?<p>As some of our customers ask during our advanced SystemVerilog/UVM training sessions, SystemVerilog doesn’t allow multiple-inheritance. Or to be precise “DID NOT have”, now in SV-2012/2013 it does!</p> <p>For those yet to get there – here is  a quick recap: </p> <p>    Simple inheritance                  Few derived classes</p> <p> <a href="http://lh3.ggpht.com/-xJzcgNSfmtU/UNuZMbBCB9I/AAAAAAAAApA/AUvKO6GmI_o/s1600-h/inh1%25255B7%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="inh1" border="0" alt="inh1" src="http://lh6.ggpht.com/-8wHG1ghJaoY/UNuZN8BznvI/AAAAAAAAApI/y-4PGJXK1iQ/inh1_thumb%25255B3%25255D.png?imgmax=800" width="122" height="172" /></a>        <a href="http://lh5.ggpht.com/-PyOrOYbliRI/UNuZU4l25EI/AAAAAAAAApQ/NzMqdeom8yY/s1600-h/inh2%25255B5%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="inh2" border="0" alt="inh2" src="http://lh5.ggpht.com/-NhaTh6Pw-IA/UNuZWQlktVI/AAAAAAAAApY/uc7K-hF4WX0/inh2_thumb%25255B1%25255D.png?imgmax=800" width="244" height="170" /></a></p> <p> </p> <p>One can of-course “derive” from another “derived class” too, as-in:</p> <p> <a href="http://lh3.ggpht.com/-q9ZiRjEWqLM/UNuZX82sDtI/AAAAAAAAApg/XG4QTbgeon8/s1600-h/inh3%25255B6%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="inh3" border="0" alt="inh3" src="http://lh4.ggpht.com/-JxsPTjJcnEA/UNuZZfkT_WI/AAAAAAAAApo/LNkIbFfqk84/inh3_thumb%25255B2%25255D.png?imgmax=800" width="152" height="244" /></a> </p> <p>This is used widely in good System Verilog code and in general any OOP code. UVM uses this a lot as many of you who have been fortunate to have attended our popular <a href="http://www.cvcblr.com/trainings" target="_blank">UVM training sessions</a> (<a title="http://www.cvcblr.com/trainings" href="http://www.cvcblr.com/trainings">http://www.cvcblr.com/trainings</a>) across the world (Yes, we have delivered across India, various cities, across the globe as in Europe, Asia etc.). </p> <p>However what was not allowed in older SystemVerilog (2005/2009) is:</p> <p>Multiple inheritance, as in:</p> <p>                                               <a href="http://lh4.ggpht.com/-HsHf52c2Ihw/UNuZa1sNXcI/AAAAAAAAAps/Hemj2VbmH7M/s1600-h/inh4%25255B5%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="inh4" border="0" alt="inh4" src="http://lh5.ggpht.com/-2XqLCp4cwbI/UNuZb7Za0xI/AAAAAAAAAp0/61C6sVZa0Fw/inh4_thumb%25255B1%25255D.png?imgmax=800" width="244" height="173" /></a> </p> <p> </p> <p>Now one may argue this is not all the time needed etc. If you need to get that interesting debate, a good starting point for you could be: <a title="http://en.wikipedia.org/wiki/Multiple_inheritance" href="http://en.wikipedia.org/wiki/Multiple_inheritance" target="_blank">http://en.wikipedia.org/wiki/Multiple_inheritance</a> </p> <p>Come to think of it, UVM supports TLM ports and that requires multiple inheritance at the core: See the UML diagram for today’s UVM TLM:</p> <p> </p> <p><a href="http://lh3.ggpht.com/-AjPCRzRHYT4/UNuZdGPjMzI/AAAAAAAAAqA/pFzfCENIOwc/s1600-h/uvm_ref_tlm_bidir_ports%25255B4%25255D.gif"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="uvm_ref_tlm_bidir_ports" border="0" alt="uvm_ref_tlm_bidir_ports" src="http://lh4.ggpht.com/-yIdYhyIFyCo/UNuZe-fB-yI/AAAAAAAAAqI/V8WlxeqMnhs/uvm_ref_tlm_bidir_ports_thumb%25255B2%25255D.gif?imgmax=800" width="611" height="341" /></a> </p> <p> </p> <p>i.e. the class <strong><em>uvm_port_base </em></strong>extends (and implements) a standard TLM-INTERFACE class (call it <strong><em>uvm_tlm_if_base</em></strong>). It is also “hierarchical” and can do better with certain characteristics of a <strong><em>uvm_component </em></strong>such as “instance path”, “parent” etc. The current UVM implementation “works-around” the limitation of SV 2005/2009 by instantiating a local <strong><em>uvm_component </em></strong>instance as a member and provides “proxy” methods to mimic the effect of multiple inheritance. </p> <p>So below is a sample code using Multiple inheritance feature that is now added to P1800-2012 SystemVerilog standard. It does so by introducing few new keywords/constructs:</p> <ul> <li><strong><em>interface class</em></strong> </li> <li><strong><em>class implements</em></strong> </li> </ul> <p>In near future your UVM base class could be remodeled as below (not full code obviously):</p> <p><a href="http://lh5.ggpht.com/-zY3l9BZk63I/UNuZf_sylsI/AAAAAAAAAqQ/lyEA8lmTIvA/s1600-h/inh_tlm2%25255B3%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="inh_tlm2" border="0" alt="inh_tlm2" src="http://lh5.ggpht.com/-UPQqnpZOl8g/UNuZhHpZjHI/AAAAAAAAAqY/Fb5Fs5afaRw/inh_tlm2_thumb%25255B1%25255D.png?imgmax=800" width="276" height="57" /></a>               <a href="http://lh4.ggpht.com/-9ghMoQ6_xfw/UNuZiQXDnZI/AAAAAAAAAqc/hMGGiqHxMtU/s1600-h/inh_tlm3%25255B2%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="inh_tlm3" border="0" alt="inh_tlm3" src="http://lh4.ggpht.com/-7LutghLblBE/UNuZjpBW5TI/AAAAAAAAAqo/nNx_dEdzpgM/inh_tlm3_thumb.png?imgmax=800" width="244" height="39" /></a> </p> <p>And voila, the <strong><em>uvm_tlm_port_base implements if_base, port_comp</em></strong>…</p> <p><a href="http://lh6.ggpht.com/-PozPevmW6t4/UNuZk2DHAUI/AAAAAAAAAqs/k7grnHUZO4c/s1600-h/inh_tlm1%25255B3%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="inh_tlm1" border="0" alt="inh_tlm1" src="http://lh3.ggpht.com/-zPhzL_UwHeM/UNuZl0OMIsI/AAAAAAAAAq4/tR-z1TZ1deE/inh_tlm1_thumb%25255B1%25255D.png?imgmax=800" width="464" height="188" /></a> </p> <p> </p> <p>As we end 2012, start pushing your friendly EDA vendor for this new stuff as early as Q1-2013! Yes, we have this running at <a href="http://www.cvcblr.com" target="_blank">CVC</a> with a popular, leading edge tool! </p> <p>Happy New Year 2013 to all our readers. Equip yourself with all updates on SystemVerilog by signing up for our upcoming sessions at CVC, contact <a href="mailto:training@cvcblr.com">training@cvcblr.com</a> for more!</p> <p> </p> <p></p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:22bbfb15-0063-40b1-aee9-92a703dc60d1" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SystemVerilog" rel="tag">SystemVerilog</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a>,<a href="http://technorati.com/tags/inheitance" rel="tag">inheitance</a>,<a href="http://technorati.com/tags/OOP" rel="tag">OOP</a>,<a href="http://technorati.com/tags/multiple+inheritance" rel="tag">multiple inheritance</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-72064615386363661002012-12-18T20:02:00.001-08:002012-12-18T20:06:54.956-08:00SV-DPI debug champion – your handy –dpiheader option<p>Ever played with SystemVerilog DPI (Direct Programming Interface)? Most of the verification engineers coming from EC/EE background, they have hard time debugging C code in general. </p> <p>Things get complicated when you deal with multi-logic-valued system such as Verilog/SV (0,1,Z,X) and 2-state system such as C. See the standard data type matching slide we deliver during our popular <a href="http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf" target="_blank">VSV training</a>: (<a title="http://www.cvcblr.com/trainings" href="http://www.cvcblr.com/trainings" target="_blank">http://www.cvcblr.com/trainings</a>):</p> <p><a href="http://lh5.ggpht.com/-jT0l2oyoi-Q/UNE77cq2VDI/AAAAAAAAAmU/i1dhhpEDGLQ/s1600-h/sv_dpi3.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="sv_dpi" border="0" alt="sv_dpi" src="http://lh3.ggpht.com/-sf8SCdeidSQ/UNE78_3iKDI/AAAAAAAAAmc/gPpfQCBrWOA/sv_dpi_thumb1.jpg?imgmax=800" width="488" height="304" /></a></p> <p> </p> <p>In case you can memorize the table above and use it each and every time when you touch DPI – perhaps you maynot need this post much. But for the 99.9% users who don’t or don’t want to do that, tools like <a href="http://www.mentor.com/products/fv/questa/" target="_blank">Questa</a> provide you a very handy option called <strong><em>-dpiheader</em></strong> Let’s see it in action: Consider a simple DPI import declaration as below:</p> <p><a href="http://lh6.ggpht.com/-_sEsaHYfioo/UNE799BFHCI/AAAAAAAAAmk/Qlr1nqxBcQg/s1600-h/dpi13.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="dpi1" border="0" alt="dpi1" src="http://lh3.ggpht.com/-4ZAZPCNXBus/UNE7_AnVhWI/AAAAAAAAAmo/419j15SLfas/dpi1_thumb1.jpg?imgmax=800" width="449" height="212" /></a> </p> <p> </p> <p>Corresponding C-code looks like:</p> <p></p> <p><a href="http://lh6.ggpht.com/-Q54gTy2LURo/UNE8AGaQM2I/AAAAAAAAAm0/6t3X6RO3ORk/s1600-h/dpi23.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="dpi2" border="0" alt="dpi2" src="http://lh3.ggpht.com/-TbwvPL-f52M/UNE8BYq42mI/AAAAAAAAAm4/GJ1iLeI9A2A/dpi2_thumb1.jpg?imgmax=800" width="448" height="196" /></a> </p> <p>So far so good? For those who have “spotted” the bug, pat yourself and continue reading. Others – any issue so far? Let’s see what the simulation output from Questa looks like:</p> <p><a href="http://lh4.ggpht.com/-uB6942c096E/UNE8Cf_FzzI/AAAAAAAAAnE/IA2hiVeyIg4/s1600-h/dpi33.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="dpi3" border="0" alt="dpi3" src="http://lh3.ggpht.com/-XjGG-dZ7GzA/UNE8DlxTnDI/AAAAAAAAAnI/DMkTYbNaETw/dpi3_thumb1.jpg?imgmax=800" width="465" height="284" /></a> </p> <p></p> <p>Now all your debug skills ON..go, chase and find that little: <img src="http://www.dan-dare.org/FreeFun/Images/CartoonsMoviesTV/BugsLifeWallpaper800.jpg" width="99" height="74" /></p> <p>If you go back to the basics – default argument data type for SV task is <strong><em>logic</em></strong> and is single bit in size. On SV side we had </p> <blockquote> <p><strong>output data)</strong></p> </blockquote> <p><strong>On C/DPI side the corresponding mapping as per LRM is:</strong></p> <p><strong></strong></p> <blockquote> <p><strong><a href="http://lh4.ggpht.com/-4yV-DcsLsgc/UNE8ETvV3UI/AAAAAAAAAnQ/1aW5fveROVc/s1600-h/dpi42.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="dpi4" border="0" alt="dpi4" src="http://lh5.ggpht.com/-Uu-aiVbl9J4/UNE8FiBpmhI/AAAAAAAAAnc/Xjc4mBfH_7o/dpi4_thumb.jpg?imgmax=800" width="244" height="83" /></a> </strong></p> </blockquote> <p></p> <p>Whereas what we intended was to use a plain “int” for “data” – the example is kind of trivial to keep things simple and in perspective. Realize that in reality this can be fairly cumbersome mapping to memorize and/or remember. </p> <p>Here is where the “debug champion” helps – your friendly –<strong><em>depheader </em></strong>option to <strong><em>vlog </em></strong>command.</p> <p><a href="http://lh6.ggpht.com/-8GtXgtxlZcc/UNE8HE1c6vI/AAAAAAAAAnk/GpmXkQ7OXQo/s1600-h/dpi63.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="dpi6" border="0" alt="dpi6" src="http://lh6.ggpht.com/-DHj6HVHJus4/UNE8IPucXjI/AAAAAAAAAns/KTtmLxiSmz4/dpi6_thumb1.jpg?imgmax=800" width="557" height="69" /></a></p> <p>When you run this, you get an output header file “<strong>sv_auto_hdrs_for_c.h</strong>”. It is best to include this to your C-code:</p> <p><a href="http://lh4.ggpht.com/-Sqnun0JYwW0/UNE8Jfj1FDI/AAAAAAAAAn0/eXXl2rEyG_8/s1600-h/dpi7%25255B7%25255D.jpg"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="dpi7" border="0" alt="dpi7" src="http://lh3.ggpht.com/-nkes3RJm3NA/UNE8Krl7jfI/AAAAAAAAAn4/eHovw22mc0A/dpi7_thumb%25255B3%25255D.jpg?imgmax=800" width="390" height="128" /></a></p> <p> </p> <p>Now during “<strong><em>vsim” </em></strong>step, the Questa invokes C-compiler and it detects the type-mismatch in arguments on SV vs. C-side. On SV side we said “output data” – indicating it is a 4-state, 1-bit variable, while on C-side we declared it as “int”:</p> <p> </p> <p><a href="http://lh3.ggpht.com/-XUPKGk_TNiU/UNE8MMQRqQI/AAAAAAAAAoE/mMzgQ5gHh6M/s1600-h/dpi8%25255B4%25255D.jpg"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="dpi8" border="0" alt="dpi8" src="http://lh4.ggpht.com/-OOqp1bVoJ94/UNE8NbBxixI/AAAAAAAAAoI/cCabKQxu9a0/dpi8_thumb%25255B2%25255D.jpg?imgmax=800" width="660" height="151" /></a> </p> <p> </p> <p>Now that’s by far a much better issue to debug than the simulation/runtime mismatch of values in C and SV side. </p> <p>So next time you attempt to use SystemVerilog DPI make sure you read this blog and use the –<strong><em>dpiheader </em></strong>option with Questa. And if your team needs experts, hands-on training on SystemVerilog, contact us via: <a href="http://www.cvcblr.com/about_us">www.cvcblr.com/about_us</a> </p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:2732fa5e-90d0-43cb-bbc9-eff354021c47" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SystemVerilog" rel="tag">SystemVerilog</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a>,<a href="http://technorati.com/tags/DPI" rel="tag">DPI</a>,<a href="http://technorati.com/tags/debug" rel="tag">debug</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-69854001903945975152012-12-17T08:53:00.001-08:002012-12-17T08:53:30.974-08:00Introducing soft constraints in SystemVerilog 2012<p>A well known aspect of constraint solving is the ability to classify hard vs. soft constraints. A quick Google search on “soft constraints” would lead you to; <a title="http://www.constraintsolving.com/tutorials/soft-constraints-tutorial" href="http://www.constraintsolving.com/tutorials/soft-constraints-tutorial" target="_blank">http://www.constraintsolving.com/tutorials/soft-constraints-tutorial</a> in case you are interested in theory.</p> <p>Taking a practical example, given the holiday season around the corner many of us would like to travel, book tickets etc. Let’s say that we want to travel from City-1 to City-2 (Say Bangalore to Chennai); the <strong><em>source</em></strong> & <strong><em>destination</em></strong> are fixed and are non-negotiable. But how we travel can be based on preference/availability/cost etc. For instance one may have options of:</p> <ul> <li>Flight </li> <li>Bus </li> <li>Train </li> <li>Car </li> </ul> <p>Now modeling the above scenario using a constraint specification language like the one in SystemVerilog, there are “constraints” as below;</p> <blockquote> <p>class my_travel_c;</p> <p>  rand places_t src, dst;</p> <p>  rand int cost;</p> <p>  rand travel_mode_t travel_mode;</p> <p>  // Non-negotiable src and dest locations</p> <p>  constraint src_dst_h { src == BLR; dst == CHENNAI;}</p> <p>  constraint minimze_cost { cost < 2000;};</p> <p>  constraint travel_preference {travel_mode inside {AIR, BUS, TRAIN};}</p> <p>endclass : my_travel_c</p> </blockquote> <p>Now depending on various factors the cost & travel-mode constraints may not be solvable. For instance if only AIR travel is desired, the cost constraint is likely to be violated. As an avid traveler you may not mind that violation and say YES it is fine! But how do you tell that to SystemVerilog? In the past one may go and turn-off the relevant/violating constraint via <strong><em>constraint_mode(0)</em></strong>;</p> <p>However that becomes tedious as before every randomize call you would need to do it (perhaps across testcases). </p> <p>Welcome the all new System Verilog 2012 soft constraint:</p> <p><a href="http://lh6.ggpht.com/-POBq3JmEaug/UM9N-kDM7cI/AAAAAAAAAlc/zg49A31c8h0/s1600-h/soft_cnst%25255B8%25255D.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="soft_cnst" border="0" alt="soft_cnst" src="http://lh5.ggpht.com/-fp0N1txdHo0/UM9OCM6xThI/AAAAAAAAAlk/kAKgsF_cM5s/soft_cnst_thumb%25255B6%25255D.jpg?imgmax=800" width="618" height="373" /></a> </p> <p>Now if the solver can satisfy the SOFT it shall, and provide you the optimal cost and travel experience. However in case it can’t, the soft can be “ignored” and other HARD constraints shall be obliged!</p> <p>Now that’s a pleasure luxury to have a set of “default” values while designing the environment and use “soft” constraints, let the tests/scenarios override the same as needed.</p> <p>BTW – this has been a widely used feature in e – IEEE-1647 language (many engineers relate it to the tool Specman, most popular implementation of the e language). So much so that a new user migrating from Specman to SystemVerilog finds it often annoying not to have this “feature”. Now, thanks to Santa in 2012, come 2013 – you will have that in SV too! Now it is time to ask for your XMAS wish with Santa and your EDA vendor to get this implemented in your favorite simulator!</p> <p>Have a pleasant journey, holidays and be ready to rock even more with all the more powerful SystemVerilog 2012 soon!</p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:590b27c1-2f93-46fe-8d0e-49b65361b0fd" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SystemVerilog" rel="tag">SystemVerilog</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-3612379846470123762012-12-11T08:55:00.001-08:002012-12-11T08:55:32.706-08:00Bringing in uniqueness constraint to SystemVerilog – welcome P1800-2012<p>If you are involved in functional verification I am sure you have atleast heard of System Verilog as the IEEE standard. The first IEEE standard was released back in 2005 and went in for a revision during 2009. Now there is yet another major update – 2012, expected to be fully ratified by early 2013 (on time for DVCon 2013). Here is a nice blog on this: <a href="http://blogs.mentor.com/verificationhorizons/blog/tag/ben-cohen/" target="_blank">http://blogs.mentor.com/verificationhorizons/blog/tag/ben-cohen/</a></p> <p>A major part of this new version is all about assertions/SVA. If you need a detailed list of changes and examples, with applications – look no further, get hold of our new SVA 3rd edition @ <a title="http://www.amazon.com/SystemVerilog-Assertions-Handbook-Edition-Verification/dp/B0096CEVQM" href="http://www.amazon.com/SystemVerilog-Assertions-Handbook-Edition-Verification/dp/B0096CEVQM" target="_blank">SVA book 3rd edition @Amazon</a></p> <p>In this article I wanted to introduce another nice, tiny, handy feature – <strong><em>unique constraint</em></strong> in SV. To give a background, consider a classical crossbar switch:</p> <p><a href="http://lh5.ggpht.com/-OSdyT6tuVFE/UMdlbooH3YI/AAAAAAAAAkQ/-ySnkLJRzz0/s1600-h/xbar_cpu_mem%25255B7%25255D.jpg"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="xbar_cpu_mem" border="0" alt="xbar_cpu_mem" src="http://lh5.ggpht.com/-lx-7IzvCs1I/UMdldaVs00I/AAAAAAAAAkY/boJd81MpqAc/xbar_cpu_mem_thumb%25255B5%25255D.jpg?imgmax=800" width="693" height="350" /></a> </p> <p> </p> <p>While every CPU can talk to/access every memory, for every access uniqueness must be maintained in terms of one-to-one connection. This is usually referred to as “Uniqueness Constraint” (ref: <a title="http://www.wonko.info/ipt/iis/infosys/infosys5.htm" href="http://www.wonko.info/ipt/iis/infosys/infosys5.htm" target="_blank">http://www.wonko.info/ipt/iis/infosys/infosys5.htm</a>). In SV 2012, with <strong><em>unique constraint </em></strong>feature one may code a transaction model for this as:</p> <p> </p> <p>  <a href="http://lh3.ggpht.com/-aX_-D-NBwpA/UMdle5OE5EI/AAAAAAAAAkg/xaSFgR7flPE/s1600-h/sv_uniq%25255B4%25255D.jpg"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="sv_uniq" border="0" alt="sv_uniq" src="http://lh3.ggpht.com/-C5EVPBy34HE/UMdlgDML_vI/AAAAAAAAAko/VSJmyWNiaeE/sv_uniq_thumb%25255B2%25255D.jpg?imgmax=800" width="579" height="307" /></a> </p> <p>One could perhaps combine this with a <strong><em>foreach </em></strong>and make it more elegant etc. But the bottomline – the <strong><em>unique </em></strong>constraint is really handy at times!</p> <p>Welcome SV 2012/2013 :-)</p> <p>Now our training in VSV (<a title="http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf" href="http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf">http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf</a>) can cover this as a lab exercise – make sure you enroll in a session to learn more! See: <a title="http://www.cvcblr.com/trainings" href="http://www.cvcblr.com/trainings">http://www.cvcblr.com/trainings</a> for more!</p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:37a0e1fe-bcef-47d2-9aa0-3ee81d236a74" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SystemVerilog" rel="tag">SystemVerilog</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-37152297652292031202012-12-07T09:12:00.001-08:002012-12-07T09:12:16.600-08:00Help yourself & UVM community by sparing few minutes – Verilab’s UVM survey<h5> </h5> <h1>UVM Runtime Phasing and Phase Jumping Survey</h1> <p>If you are well aware of UVM runtime phasing/phase jumping issues, quickly help yourself and the UVM community at large by filling out this survey:</p> <ul> <li><a href="https://www.surveymonkey.com/s/verilab-uvm-phasing-survey-cv">Verilab UVM Phasing Survey</a> </li> </ul> <p>Now for a background and for those who are “undecided” whether or not I have an issue with it, here is more information:</p> <p>One of the significant updates done to OVM while bringing up UVM as the standard for verification methodology was the phasing. (For a detailed paper on user issues with OVM phasing approach, see: <a title="http://www.synopsys.com/community/snug/india/pages/abstracts.aspx?loc=india&locy=2011" href="http://www.synopsys.com/community/snug/india/pages/abstracts.aspx?loc=india&locy=2011">http://www.synopsys.com/community/snug/india/pages/abstracts.aspx?loc=india&locy=2011</a> and <a title="https://www.synopsys.com/news/pubs/snug/india2011/TA1.2_Intel_paper.pdf" href="https://www.synopsys.com/news/pubs/snug/india2011/TA1.2_Intel_paper.pdf">https://www.synopsys.com/news/pubs/snug/india2011/TA1.2_Intel_paper.pdf</a>) </p> <p>As with any standard development, there are differing view points coming from various experts, users etc. around the globe.India being the most vibrant Verification geography, it is very probable that many of the verification leads here face these problems day-in and day-out. So why not speak up and help us fix the UVM phasing the way YOU would like it?</p> <p><a href="http://www.verilab.com" target="_blank">Verilab</a>, a premier verification consulting firm based in the US is conducting a survey to find out whether UVM users are currently taking advantage of runtime phasing and phase jumps, and if so, whether or not they would be impacted by certain changes the committee might propose. </p> <p>So in case you are an active user of UVM, please spare a few minutes and take the survey at:</p> <ul> <li><a href="https://www.surveymonkey.com/s/verilab-uvm-phasing-survey-cv">Verilab UVM Phasing Survey</a> </li> </ul> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:d59f3d07-4c8c-43cb-b44c-b295449bbfc1" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/UVM" rel="tag">UVM</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a>,<a href="http://technorati.com/tags/VIP" rel="tag">VIP</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-68096261584839241672012-12-04T09:43:00.001-08:002012-12-04T09:43:54.406-08:00Is my SystemVerilog mailbox half-full or half-empty? An engineer’s hunger now served!<p>As we wrap up 2012 with yet another successful <a href="http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf" target="_blank">VSV course</a> at <a href="http://www.cvcblr.com" target="_blank">CVC</a> today’s  topic was IPC in System Verilog. As most of the attendees in this session are young engineers, they have a constant thirst for knowledge and demand more. We at CVC love that challenge. Based on last few sessions we created more smaller examples around threads, mailboxes for the engineers to play around with. Here are some of the meddling around experiments you may do with Mailboxes in SV.</p> <p>To start with – the size of the mailbox – a.k.a the DEPTH of the FIFO: Here is how you configure the same (the formal argument is named as <strong><em>bound </em></strong>by LRM):</p> <p><a href="http://lh3.ggpht.com/-PsCV0hdlgUc/UL42JvBuOII/AAAAAAAAAiI/hEpJirE1HEw/s1600-h/mbx1%25255B4%25255D.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="mbx1" border="0" alt="mbx1" src="http://lh5.ggpht.com/-BLAyc2LAiBc/UL42KpfUAzI/AAAAAAAAAiQ/yi-kR-Y34pc/mbx1_thumb%25255B2%25255D.jpg?imgmax=800" width="466" height="189" /></a> </p> <p>And we had some interesting discussion around the <strong><em>bound </em></strong>& <strong><em>num()</em></strong>  - similar to FIFO’s DEPTH and LEVEL:</p> <p>To get the code part of it straight, here is what LRM has on these 2 methods:</p> <blockquote> <p><font size="4">function new (int bound = 0);</font></p> </blockquote> <p>i.e. the constructor for mailbox has an argument that’s defaulted to 0 – be careful with it, this could lead to memory leaks from user code (See: <a title="http://www.cvcblr.com/blog/?p=29" href="http://www.cvcblr.com/blog/?p=29">http://www.cvcblr.com/blog/?p=29</a> )</p> <p>The summary there – use sized mailbox always. This would fix the DEPTH of the FIFO or the Mailbox:</p> <p><a href="http://lh6.ggpht.com/-oyMjvVpPLh4/UL42Lu8RjkI/AAAAAAAAAiY/1v8pZezldtM/s1600-h/mb_empty%25255B3%25255D.jpg"><img style="border-right-width: 0px; display: block; float: none; border-top-width: 0px; border-bottom-width: 0px; margin-left: auto; border-left-width: 0px; margin-right: auto" title="mb_empty" border="0" alt="mb_empty" src="http://lh4.ggpht.com/-K4I67-3Hks8/UL42MvWrhCI/AAAAAAAAAic/zpvdOLqvwAc/mb_empty_thumb%25255B1%25255D.jpg?imgmax=800" width="246" height="144" /></a></p> <p>Now there is a method to get the “current level” of the Mailbox, with prototype:</p> <blockquote> <p> <font size="4">function int num ();</font></p> </blockquote> <p>Here is a pictorial way to explain its usage:</p> <p> </p> <blockquote> <p><a href="http://lh5.ggpht.com/-NNIfpM5mweE/UL42Nr30xBI/AAAAAAAAAio/XTN9G8OBRdg/s1600-h/mb_alm_emp%25255B3%25255D.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="mb_alm_emp" border="0" alt="mb_alm_emp" src="http://lh3.ggpht.com/-6b4cPnMC_xk/UL42OxHpKVI/AAAAAAAAAiw/d2oOgXJyB2M/mb_alm_emp_thumb%25255B1%25255D.jpg?imgmax=800" width="246" height="159" /></a>                        <a href="http://lh4.ggpht.com/-DRCrKLzCGz8/UL42P16iBkI/AAAAAAAAAi0/zi702WPU5u0/s1600-h/mb_alm_full%25255B3%25255D.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="mb_alm_full" border="0" alt="mb_alm_full" src="http://lh3.ggpht.com/-Cf5MQiE386Q/UL42Q1a5bzI/AAAAAAAAAjA/py_USqjvHnM/mb_alm_full_thumb%25255B1%25255D.jpg?imgmax=800" width="246" height="159" /></a>       <a href="http://lh5.ggpht.com/-ToMhVdYp_3Y/UL42SAtWbxI/AAAAAAAAAjI/4SG6fHlxSjE/s1600-h/mb_full%25255B4%25255D.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="mb_full" border="0" alt="mb_full" src="http://lh3.ggpht.com/-Ac-1rhIgSyc/UL42TA647zI/AAAAAAAAAjQ/sAaKRW4KHpg/mb_full_thumb%25255B2%25255D.jpg?imgmax=800" width="246" height="159" /></a></p> </blockquote> <p></p> <p></p> <p></p> <p></p> <p></p> <p> </p> <p>To look at some SystemVerilog code:</p> <p><a href="http://lh6.ggpht.com/-7MC5SDsk2b8/UL42Ui9191I/AAAAAAAAAjY/56ReIZJekn0/s1600-h/mbx2%25255B5%25255D.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="mbx2" border="0" alt="mbx2" src="http://lh6.ggpht.com/-nduFQaPmZbQ/UL42V1U0g8I/AAAAAAAAAjg/ED89qR429wM/mbx2_thumb%25255B3%25255D.jpg?imgmax=800" width="700" height="397" /></a> </p> <p>And to close this article with more pictures than usual – be careful with generic mailboxes – i.e. those with no explicit parameterization. Avoid them if you can, watch this space <a href="http://www.cvcblr.com/blog" target="_blank">www.cvcblr.com/blog</a> for an upcoming article on that.</p> <p>Do more with SystemVerilog! And do call us via <a href="mailto:training@cvcblr.com">training@cvcblr.com</a> in case you want to learn SystemVerilog the right way!</p> <p> </p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:870f3239-af59-4952-a5a7-fe9d351b54db" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SystemVerilog" rel="tag">SystemVerilog</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a>,<a href="http://technorati.com/tags/training" rel="tag">training</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-78626291571876728282012-11-20T09:18:00.001-08:002012-11-20T09:18:30.471-08:00Easier PLI integration with MPSim<p>Several engineers working and aspiring to work in the field of ASIC front-end design/verification tend to stay away from Verilog’s powerful PLI/VPI – some of them because they see it as old technology and many others – simply “FEAR” from it, thanks to its complex integration with the tools. </p> <p>For those who believe it is old technology – think again, most of the cutting edge EDA innovations (in front end) happening around verification use Verilog’s PLI/VPI to talk to your underlying simulator. To quote a few examples:</p> <ol> <li><a href="http://www.nextopsoftware.com" target="_blank">NextOp</a>/Atrenta’s <a href="http://www.cvcblr.com/blog/?p=473" target="_blank">BugScope</a>  </li> <li>Novas’s Verdi/Debussy </li> <li>Axiom’s @Designer <a href="http://www.axiom-da.com">http://www.axiom-da.com</a> (Debugger that can work with all standard Verilog simulators) </li> <li>Trek from Brekersystems (<a href="http://www.brekersystems.com">www.brekersystems.com</a>) </li> <li>OnPoint from vennsa-da.com </li> </ol> <p>Now for those who “fear” from VPI due to its integration challenges – to be fair – you’ve reasons to do so. However advanced functional verification solutions such as VCS, MPSim (<a href="http://www.axiom-da.com">http://www.axiom-da.com</a> ) provide a convenient TABLE format to ease this task. All you need to do is to create the following table:</p> <p><a href="http://lh4.ggpht.com/-AoCNsJtQRfQ/UKu7SacPLTI/AAAAAAAAAgw/IS1Hul7pcGk/s1600-h/mpsim_tab%25255B6%25255D.gif"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="mpsim_tab" border="0" alt="mpsim_tab" src="http://lh3.ggpht.com/-stbcPkXniZ0/UKu7TwxoJSI/AAAAAAAAAg4/rvCZwo2nW2A/mpsim_tab_thumb%25255B4%25255D.gif?imgmax=800" width="516" height="209" /></a> </p> <p>And use standard gcc to compile your C-code as below:</p> <blockquote> <p><strong><font size="3">gcc -m32 -pipe -c -g ../pr_tscale.c -I$(ATHDLROOT)/tb/incl –DAXIOM <br /></font></strong></p> </blockquote> <p>Now, invoke the <strong><em>atsim</em></strong> compiler with the <strong><em>tab</em></strong>-file as shown in below command:</p> <blockquote> <p><strong><font size="3">atsim -c ../pr_tscale.v +tabfile+pr_tscale.tab +pliobj+../pr_tscale.o <br />./athdl_sv </font></strong></p> </blockquote> <p> </p> <p>For those trying it out at your end, notice the path to the *.o file should have “<strong><em>../”</em></strong> as the atsim compiled one-dir below (hidden dir).</p> <p>Now if it was this simple, why would anyone <strong>FEAR</strong>  <img src="http://i1196.photobucket.com/albums/aa411/Gil_Zilberfeld/courage.jpg" width="201" height="165" /> from it really? The answer is – that’s how the Verilog LRM defines it to be, see below if you have time and patience. Advanced verification platforms like <a href="http://www.axiom-da.com/products.html" target="_blank">MPSim</a> will hide these details for you for your pleasure adn ease-of-use! </p> <p>For those uninitiated with this <strong>fear</strong>, see how the Verilog LRM defines a data structure for this purpose below: (extract from standard vpi_user.h)</p> <p> </p> <p> <a href="http://lh5.ggpht.com/-71NXQDda-N0/UKu7VPS5luI/AAAAAAAAAhA/uWdOvsgtMkg/s1600-h/vpi_systf%25255B6%25255D.gif"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="vpi_systf" border="0" alt="vpi_systf" src="http://lh6.ggpht.com/-8wT5pk9KZEE/UKu7WEUK_dI/AAAAAAAAAhI/gn0NiNW7adI/vpi_systf_thumb%25255B4%25255D.gif?imgmax=800" width="689" height="282" /></a> </p> <p> </p> <p>Now to use it in an end-user application such as the one found at: <a title="http://www.cvcblr.com/blog/?p=517" href="http://www.cvcblr.com/blog/?p=517">http://www.cvcblr.com/blog/?p=517</a> one needs to create a variable of this structure and fill in the integration details, see below:</p> <p><a href="http://lh4.ggpht.com/-wdIu_cqY4Dg/UKu7XmvmDjI/AAAAAAAAAhQ/XKNbvbQ8o_s/s1600-h/vlog_startup%25255B7%25255D.gif"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="vlog_startup" border="0" alt="vlog_startup" src="http://lh6.ggpht.com/-Ku5S5Q9hg7o/UKu7YxVrLtI/AAAAAAAAAhU/DgtananXrXI/vlog_startup_thumb%25255B5%25255D.gif?imgmax=800" width="530" height="506" /></a> </p> <p>If you managed to read up to this – then you are convinced that integration of VPI code isn’t for everyone – if not for tools like <a href="http://www.axiom-da.com/products.html" target="_blank">MPSim</a> !</p> <p>Good Luck!</p> <p><a href="http://www.cvcblr.com" target="_blank">TeamCVC</a> </p> <p></p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:4e5aa01a-d451-4b3d-8f0f-722624b4e9fc" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/Verilog" rel="tag">Verilog</a>,<a href="http://technorati.com/tags/PLI" rel="tag">PLI</a>,<a href="http://technorati.com/tags/VPI" rel="tag">VPI</a>,<a href="http://technorati.com/tags/MPSim" rel="tag">MPSim</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-74863879966918855292012-10-10T13:31:00.001-07:002012-10-10T13:31:18.829-07:00Reducing power in a smartphone – who-will-bell-the-cat? – Possible answers from ARM<p>Earlier this week, Simon Segars, EVP & GM Processor and Physical IP Divisions (<a href="http://linkd.in/ThbmbZ" target="_blank">http://linkd.in/ThbmbZ</a>) presented an excellent keynote at an invite-only, executive dinner event around the CDNLive India 2012 <a href="http://bit.ly/TxallC">http://bit.ly/TxallC</a> organized by Cadence. Our CTO Srini (<a href="http://linkd.in/e6cSbd" target="_blank">http://linkd.in/e6cSbd</a>)</p> <p>His theme was around the low power requirements in modern mobile devices (understandably, as the market needs this topic and who is in a better position than ARM can talk about this – being at the center of most of those smartphones!)</p> <p>In a well drafted, upto-the-point, picture-centric presentation Simon did a great job of explaining what ARM’s <strong><em>big.LIITLE </em></strong>architecture is all about! </p> <p>As of today, ARM provides Cortex A-15 like cores for the high-end devices:</p> <p><a href="http://lh3.ggpht.com/-y7PGte71en8/UHXayiUHAhI/AAAAAAAAAfI/RxV2XqShrBY/s1600-h/image%25255B3%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh3.ggpht.com/-XMeKqpJoDKQ/UHXa0QiU_5I/AAAAAAAAAfQ/stIjnYoDjlQ/image_thumb%25255B1%25255D.png?imgmax=800" width="728" height="209" /></a> </p> <p> </p> <p>Quickly ARM realized there is a strong need for low-energy, low-cost cores too to serve the entry level smartphones – here comes the ARM Cortex A-7</p> <p><a href="http://lh6.ggpht.com/-3gvtuo_ePrY/UHXa16xZ30I/AAAAAAAAAfU/_INQC5KxdhY/s1600-h/image%25255B7%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh6.ggpht.com/-3zvJlsnw5yY/UHXa3m6OwFI/AAAAAAAAAfg/tf6zFxMTimc/image_thumb%25255B3%25255D.png?imgmax=800" width="730" height="201" /></a> </p> <p> </p> <p>Now with lot of data mining and analysis Simon showed a typical pattern that revealed 2 important data points:</p> <ol> <li>For a whopping <strong>88% </strong>of the time in a day, the kind of applications that are run on a smartphone can be done using a processor with speed < 500 MHz </li> <li>For the remaining <strong>12%</strong> the frequency needs to be > 500 MHz – these are the videos, gaming etc. </li> </ol> <p>Agreed, your numbers may vary, but the fundamental point is – one could do lot of power saving if we have a <strong>big </strong>processor to serve the high-end apps and a <strong>LITTLE </strong>processor to attend to the regular, most-of-the-day work such as MP3 playback, phone calls etc.And this is precisely what ARM’s <strong>big.LITTLE </strong>architecture is all about – have dual cores with Cortex A-7 & Cortex A-15. I found a slightly older slide on a quick Google search as below (Simon had an updated version of the same)</p> <p><a href="http://lh5.ggpht.com/-TY-ofEIgodA/UHXa55BkJZI/AAAAAAAAAfo/HJ2ER0eTUHo/s1600-h/image%25255B12%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh4.ggpht.com/-X_6pk4hAkxw/UHXa8jukUBI/AAAAAAAAAfw/6Q2V5HOWSLI/image_thumb%25255B6%25255D.png?imgmax=800" width="730" height="392" /></a> </p> <p> </p> <p><a href="http://lh6.ggpht.com/-_zblM9ksroo/UHXa-n5KuGI/AAAAAAAAAf4/zGb2kz9E5VE/s1600-h/image%25255B20%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh5.ggpht.com/-yJVtjZPFhio/UHXbAbtu5sI/AAAAAAAAAgA/DSzRxvF1X6I/image_thumb%25255B10%25255D.png?imgmax=800" width="732" height="444" /></a> </p> <p>Now of-course you need multiple teams to take advantage of such an architecture to deliver low power promise to the end user. Simon showed a nice slide listing some of the key stakeholder/steps:</p> <ul> <li>The system architects to decide which app will run on which core </li> <li>The underlying OS to be able to support such a live-scheduling </li> <li>The design team to design and implement the various low power techniques such as the DVFS </li> <li>The all the more important DV team doing the functional Verification to ensure all the valid power state scenarios are working fine </li> <li>Backend team to implement the intended power-save architecture in layout </li> <li>Circuit designers to do their bit in choosing various low level power saving techniques </li> </ul> <p><a href="http://lh3.ggpht.com/-MkElU5xt__8/UHXbC4kSxGI/AAAAAAAAAgE/ru15o3iVbAM/s1600-h/image%25255B15%25255D.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="image" border="0" alt="image" src="http://lh6.ggpht.com/-sZvDr0FahMM/UHXbEqCG4ZI/AAAAAAAAAgQ/fj_ANrDpxWQ/image_thumb%25255B7%25255D.png?imgmax=800" width="244" height="196" /></a> </p> <p>Now going back to our starting question of “Who-will-bell-the-cat” of that “<strong>magical low power smartphone chip”</strong> – Simon concluded it is <strong>ALL-of-us</strong> together who need to do this – can’t achieve this level of gains without collaboration!</p> <p>We at <a href="http://ww.cvcblr.com" target="_blank">CVC</a> are doing our part of the ecosystem work by developing advanced low power verification training on UPF, CPF modeling, case studies on a UVM SoC Kit etc. So if you are in need of verification training on any of these topics, call us via +91-80-42134156 or <a href="mailto:training@cvcblr.com">training@cvcblr.com</a> </p> <p> </p> <p></p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:d6f8d042-2eb4-45c8-a85c-59a8b586cbcf" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/Low+Power" rel="tag">Low Power</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a>,<a href="http://technorati.com/tags/ARM" rel="tag">ARM</a>,<a href="http://technorati.com/tags/Cortex" rel="tag">Cortex</a>,<a href="http://technorati.com/tags/UPF" rel="tag">UPF</a>,<a href="http://technorati.com/tags/CPF" rel="tag">CPF</a>,<a href="http://technorati.com/tags/UVM" rel="tag">UVM</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com1tag:blogger.com,1999:blog-7343793379868603098.post-4736692690569600052012-09-04T09:39:00.001-07:002012-09-04T09:39:41.419-07:00Upgrade yourself to SystemVerilog 2012 – our SVA handbook, 3rd edition is published!<p>They say “<strong>innovation never stops</strong>” – it is true for the SystemVerilog language committee. And it is very true for our co-author Ben Cohen, who even at the retired age keeps updating himself on latest on SV, VMM, OVM, UVM and of-course SVA. Ben Cohen is the Accellera nominated representative for the SV-AC committee on IEEE dev team. </p> <p>See TOC at: <a href="http://systemverilog.us/SVA3rdE_preface_toc.pdf">http://systemverilog.us/SVA3rdE_preface_toc.pdf</a></p> <p>The cover of this book is a NASA photograph of Mars, taken by Curiosity. Just like how Mars is enormously big, the verification state space of most of the modern day designs are extremely large. While there have been several advances in the area of "stimulus" or "activation of potential design errors", the amount of checking being done during such activation (either via simulation or formal analysis) demands detailed, precise design specification. This is precisely where SVA fits in the design flow. Just like how the whole world awaits pictures & findings from Curiosity to learn more about Mars, SVA could be used by the design verification teams to learn about the functional quality of designs.</p> <p><a href="http://lh6.ggpht.com/-YmkAjFtrV2g/UEYulL-bxDI/AAAAAAAAAdw/_FZ-RhH0kJA/s1600-h/sva3rdE_cover%25255B5%25255D.jpg"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="sva3rdE_cover" border="0" alt="sva3rdE_cover" src="http://lh5.ggpht.com/-PtQmnXecxhA/UEYumrnEL1I/AAAAAAAAAd4/8Ly59e6tMLU/sva3rdE_cover_thumb%25255B3%25255D.jpg?imgmax=800" width="646" height="519" /></a> </p> <p>Here is what the forewords say:</p> <p><strong><u>Dennis Brophy </u></strong>Director of Strategic Business Development, Mentor Graphics. </p> <p align="center"> </p> <p><a href="http://lh3.ggpht.com/-Fp4Kq6eyqj8/UEYunvLmJAI/AAAAAAAAAeA/ZfG5xvNpR3M/s1600-h/MENT_logo%25255B2%25255D.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="MENT_logo" border="0" alt="MENT_logo" src="http://lh3.ggpht.com/-bOGlrk6n0ks/UEYupO40LoI/AAAAAAAAAeI/K59unBnsDdA/MENT_logo_thumb.jpg?imgmax=800" width="244" height="83" /></a> <br /></p> <blockquote> <p>In 2010, research showed use of <strong>SystemVerilog was up more than 233%</strong> over prior years with more than 7 out of 10 design and verification engineers using it. Even more telling was the use of the SystemVerilog Assertions (SVA) part of the standard. Research showed that assertions enjoyed the same high level of use with <strong>7 out of 10 design and verification engineers adopting SVA</strong>. <br />Assertion based verification (ABV) methodologies has been found to address design and verification challenges and the market use reflects it. The assertions portion of the IEEE SystemVerilog standard has also been enhanced over these years to extend and improve what can be done with them based on the cumulative experiences of the design and verification community to date.</p> <p> <br />The third edition to the SystemVerilog Assertions Handbook comes at a time when the IEEE updates its popular SystemVerilog standard and at a time when the FPGA community is increasing its adoption of SystemVerilog assertions as well. Design and verification engineers will find the handbook useful not just as a resource to begin to adopt assertions, but to apply the latest additions and updates found in the IEEE standard to the ever pressing design and verification challenges.</p> <p> </p> </blockquote> <p> </p> <p align="center"><strong><u>Sven Beyer, </u></strong>Product Manager Design Verification, OneSpin Solutions</p> <p> <br /><a href="http://www.onespin-solutions.com/">http://www.onespin-solutions.com/</a></p> <p><a href="http://lh5.ggpht.com/-7TuwZdX28Gs/UEYuqW55JxI/AAAAAAAAAeQ/wenUfIrowJQ/s1600-h/OneSpin_logo%25255B2%25255D.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="OneSpin_logo" border="0" alt="OneSpin_logo" src="http://lh6.ggpht.com/-DaJnJS7fhxg/UEYuraWCRTI/AAAAAAAAAeY/VtEgpkuN7gU/OneSpin_logo_thumb.jpg?imgmax=800" width="171" height="64" /></a> </p> <blockquote> <p>The SystemVerilog standard itself has been very much alive with two updates in 2009 and now in 2012, enhancing many existing features and adding numerous new ones. So more and more engineers are exposed to SVA while at the same time, the standard quickly evolves, trying to address the growing needs of those engineers for more productivity. This definitely calls for a first class reference documentation – and this book, <strong>SystemVerilog Assertions Handbook, 3rd Edition by Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari, and Lisa Piper,</strong> provides such a comprehensive reference manual that is suited for both SVA power users and novices. It introduces assertion methodologies and gives a clear idea on what assertions are good for,addressing both coverage and the complementary strengths of dynamic and formal verification. It carefully <br />lays out the numerous SVA language constructs one by one in a way that really gets across to the typical engineer, emphasizing the intended usage, adding telling examples, and listing the counter-intuitive pitfalls that may cost an engineer precious time in debugging. Therefore, this book is sure to find its place on the bookshelf of numerous engineers all over the world, and since it is the first comprehensive reference manual to also address the IEEE 1800-2012 standard, for example with its numerous enhancements to the checker construct, it is sure to remain on this shelf and be extensively used for quite some time.</p> </blockquote> <p> </p> <p><strong><u>Stuart Sutherland , </u></strong>SystemVerilog Training and Consulting Wizard <br />Sutherland HDL, Inc. <br />http://www.sutherland-hdl.com</p> <p><strong><u><a href="http://lh3.ggpht.com/-KlDUkjTRNvI/UEYuxkvWRoI/AAAAAAAAAeg/HGAASCdfvCs/s1600-h/Stuart_logo%25255B2%25255D.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="Stuart_logo" border="0" alt="Stuart_logo" src="http://lh6.ggpht.com/-z2NotXdeyQM/UEYuynL5O7I/AAAAAAAAAeo/8mIPXLI84gI/Stuart_logo_thumb.jpg?imgmax=800" width="244" height="132" /></a> <br /></u></strong></p> <blockquote> <p>The complexity of the design we need to verify requires that an assertions language has a robust set of features and capabilities. The SystemVerilog Assertions (SVA) language meets that rigorous requirement. The robustness of SVA also means that it can be challenging to learn to use SVA -- and to use it correctly. The SystemVerilog Assertions Handbook is an essential resource for overcoming that challenge. The book examines the use of SVA in the context of verifying true-to-life designs. Thorough explanations of each feature of SVA show the where and how to use SVA correctly, as well as point out pitfalls to avoid. At my company, we feel this book is so essential for understanding and properly using SVA, that we include a copy of the book as part of the standard training materials in all of our “SystemVerilog Assertions for Design and Verification Engineers” training workshops. <br /></p> </blockquote> <p><strong><u>Cristian Amitroaie </u></strong>CEO, Amiq</p> <p><img alt="http://www.dvteclipse.com/img/log/AMIQ_EDA_logo__s1.jpg" src="http://www.dvteclipse.com/img/log/AMIQ_EDA_logo__s1.jpg" width="215" height="72" />.</p> <blockquote> <p>The first benefit this book brings is a systematic and clearly organized perspective on SVA, from planning to terminology, from how assertions work and how to debug them, to coverage driven and formal verification using assertions. This includes the language clearly identified rules, and many tables and figures annotated with comments.</p> <p> <br />Second it offers many concrete examples. Examples are fresh air for engineers when diving into complex topics and this book has plenty, including the mapping between natural language and the corresponding SVA implementation.</p> <p> <br />Third, it contains guidelines on what to use and what to avoid, based on experience with both SVA and UVM. Knowing and following best practices are essential to engineers these days, when work pressure doesn't leave much time to carefully digest all the implications of the highly sophisticated means we use on a daily basis.</p> <p> <br /><strong>This is a book every engineer should keep handy</strong>! <br /></p> </blockquote> <p></p> <p></p> <p></p> <p></p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:d4533918-1485-4dc4-8623-c0075f406211" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SVA" rel="tag">SVA</a>,<a href="http://technorati.com/tags/Assertions" rel="tag">Assertions</a>,<a href="http://technorati.com/tags/SystemVerilog+Verilog+EDA" rel="tag">SystemVerilog Verilog EDA</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-65258739177550512842012-08-20T07:24:00.001-07:002012-08-20T07:24:27.460-07:00Visualizing SystemVerilog event regions<p>One of the strengths of assertions in SystemVerilog is its well defined sampling semantics. Though it works out-of-the-box and is robust, many users don’t seem to understand it in depth. As we have been blogging on assertions – one needs to be very “pedantic”, i.e. detail oriented to be able to appreciate it, demonstrate it and understand it. </p> <p>We at <a href="http://www.cvcblr.com" target="_blank">TeamCVC</a> have been pioneering assertions as a focus area since our PSL book days (end of 2003, <a href="http://www.systemverilog.us/psl_info.html">http://www.systemverilog.us/psl_info.html</a>) and it has been almost a decade by now! We cover this in all our training sessions on assertions such as: </p> <ul> <li>SVA: <a title="http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf" href="http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf">http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf</a></li> <li>PSL: <a title="http://www.cvcblr.com/trng_profiles/CVC_LG_PSL_profile.pdf" href="http://www.cvcblr.com/trng_profiles/CVC_LG_PSL_profile.pdf">http://www.cvcblr.com/trng_profiles/CVC_LG_PSL_profile.pdf</a></li> </ul> <p>Even during our popular VSV course (<a title="http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf" href="http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf">http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf</a>) we touch upon this topic during the <strong><em>program </em></strong>block discussion. Below is an extract from our training/book on SVA (<a href="http://www.systemverilog.us/sva_info.html">http://www.systemverilog.us/sva_info.html</a>):</p> <p> </p> <p><a href="http://lh3.ggpht.com/-JRh5dNnBswg/UDJIHhGihCI/AAAAAAAAAbw/KJdQsEd1VeE/s1600-h/SV_event_regions%25255B4%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="SV_event_regions" border="0" alt="SV_event_regions" src="http://lh5.ggpht.com/-FNYR7B4xPls/UDJIJF5Wh2I/AAAAAAAAAb4/2OJW6iZEaX4/SV_event_regions_thumb%25255B2%25255D.png?imgmax=800" width="608" height="382" /></a> </p> <p> </p> <p>While the above slide goes well into the depth of this topic, often users ask us if they could “visualize it” inside waveform. Recently we did a SVA class for a VHDL customer who use Questa. Being part of QVP <a href="http://www.mentor.com/products/fv/partners/qvp">http://www.mentor.com/products/fv/partners/qvp</a> we at <a href="http://ww.cvcblr.com" target="_blank">CVC</a> have access to Mentor’s latest technologies and this customer insisted that we use Questa during the labs. We enabled more debug sessions including their famous Questa ATV (<em>Assertion Thread Viewer</em>) feature. One of the nice examples our <a href="http://www.cvcblr.com" target="_blank">TeamCVC</a> have created explains the events/time-regions nicely. See below for a screenshot:</p> <p><a href="http://lh4.ggpht.com/-Q6de_YPN2n8/UDJIKko_MqI/AAAAAAAAAcA/ylVU3MHXXkg/s1600-h/Picture1%25255B8%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="Picture1" border="0" alt="Picture1" src="http://lh6.ggpht.com/-7ULmBPc1MCM/UDJINCMP6HI/AAAAAAAAAcI/8HHlMkVuzzA/Picture1_thumb%25255B16%25255D.png?imgmax=800" width="624" height="236" /></a> </p> <p></p> <p> </p> <p>It is almost the same as SystemVerilog LRM’s event Queue – brought inside the waveform, isn’t it! Here is a code snippet for the RTL regions such as “ACTIVE, INACTIVE & NBA” – this is same as in plain Verilog BTW:</p> <p><a href="http://lh6.ggpht.com/-Qku1mYDbwRk/UDJIObo2zfI/AAAAAAAAAcQ/WCIdl0EuKOQ/s1600-h/rtl_regions%25255B5%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="rtl_regions" border="0" alt="rtl_regions" src="http://lh4.ggpht.com/-KW6DNiXn80Q/UDJIPm-P5zI/AAAAAAAAAcY/f_wxBi2CzwQ/rtl_regions_thumb%25255B3%25255D.png?imgmax=800" width="695" height="214" /></a> </p> <p> </p> <p>Now recall that in testbench with System Verilog there is a <strong><em>program </em></strong>block that executes in REACTIVE region. And so are the assertion action-blocks. And within <strong><em>program </em></strong>block one can do blocking, #0 and NBA ssigns. So how does that get scheduled? </p> <p><a href="http://lh4.ggpht.com/-Q6de_YPN2n8/UDJIKko_MqI/AAAAAAAAAcg/zmGNWhCUwUw/s1600-h/Picture1%25255B10%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="Picture1" border="0" alt="Picture1" src="http://lh6.ggpht.com/-7ULmBPc1MCM/UDJINCMP6HI/AAAAAAAAAck/rp8h9X-v1ZY/Picture1_thumb%25255B23%25255D.png?imgmax=800" width="670" height="252" /></a> </p> <p> </p> <p>And relevant code-snippet for the REACTIVE assignments:</p> <p> </p> <p><a href="http://lh3.ggpht.com/-5kCwsJXH5yY/UDJIT4vpOtI/AAAAAAAAAco/CGy4cpS8EUk/s1600-h/pgm_regions%25255B5%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="pgm_regions" border="0" alt="pgm_regions" src="http://lh4.ggpht.com/--vTGz2DHdCI/UDJIaRYEXmI/AAAAAAAAAcw/ShKMOHflE8k/pgm_regions_thumb%25255B6%25255D.png?imgmax=800" width="655" height="156" /></a> </p> <p></p> <p> </p> <p>Putting the full waveform:</p> <p><a href="http://lh6.ggpht.com/-_XTPJldjBfU/UDJIhro9QCI/AAAAAAAAAc4/1c1bbu7obkg/s1600-h/Picture1%25255B14%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="Picture1" border="0" alt="Picture1" src="http://lh3.ggpht.com/-oR41vIxxqFQ/UDJIipAOkGI/AAAAAAAAAdA/gY_LAgj_--g/Picture1_thumb%25255B25%25255D.png?imgmax=800" width="685" height="166" /></a> </p> <p> </p> <p>NOTE: the “time” doesn’t advance, it is only the <strong>DELTAs – Questa </strong>is powerful indeed in visualizing it, we will try and add other tool screenshots in near future if there is enough demand from you – our beloved readers!</p> <p>Before we close, here is what a full, IDE (Integrated Development Environment) that Questa provides for this:</p> <p><a href="http://lh5.ggpht.com/-HP2oAo6TIj0/UDJIkTX55AI/AAAAAAAAAdI/Tun20o1bBOY/s1600-h/image%25255B9%25255D.png"><img style="border-bottom: 0px; border-left: 0px; display: inline; border-top: 0px; border-right: 0px" title="image" border="0" alt="image" src="http://lh6.ggpht.com/-rSUD19wKj2g/UDJImImHtaI/AAAAAAAAAdQ/h78lgreYop0/image_thumb%25255B8%25255D.png?imgmax=800" width="643" height="409" /></a> </p> <p></p> <p>Hope you enjoyed this “flow of events” and the power of “visualizing” it – as much as we did. Drop your comments below!</p> <p>Signing off with confidence, it is <a href="http://www.cvcblr.com" target="_blank">TeamCVC</a>!</p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:8642e2b6-5aa0-4e89-ad6c-56977c54b51c" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/SVA" rel="tag">SVA</a>,<a href="http://technorati.com/tags/SystemVerilog+Verilog+EDA" rel="tag">SystemVerilog Verilog EDA</a>,<a href="http://technorati.com/tags/Verilog" rel="tag">Verilog</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a>,<a href="http://technorati.com/tags/Questa" rel="tag">Questa</a>,<a href="http://technorati.com/tags/Debug" rel="tag">Debug</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com0tag:blogger.com,1999:blog-7343793379868603098.post-66587095184473993042012-08-19T09:56:00.001-07:002012-08-19T09:56:39.743-07:00Verilog PLI/VPI – a sample tree walker + hierarchical print_timescale app!<p>Here is a nice Verilog VPI (Verilog Procedural Interface a.k.a PLI 2.0) app that we mentioned during our just concluded Verilog training at <a href="http://ww.cvcblr.com" target="_blank">CVC</a>. </p> <p>This application just walks through the complete design hierarchy and spits out the Timescale information for each module. It is quite handy to find which module has the least timescale precision value (and hence controls the whole simulation) for e.g. when the design has been given as a compiled database or a protected one – simple grep/PERL kind of ideas maynot fit. This application will extract:</p> <ol> <li>The module name </li> <li>Its Time Scale value </li> <li>Its TimePrecision value </li> </ol> <p>Here is a PLI task named " $print_timescale " which if called on a top level module will print this information for the entire hierarchy.</p> <p>The following Verilog code (which could be the top level of your design, or TB) shows how to use such a task. </p> <p> </p> <p><a href="http://lh6.ggpht.com/-XRhgVhvI8lI/UDEamkfOToI/AAAAAAAAAZ4/0XXN4IIWHPo/s1600-h/vlog_top5.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="vlog_top" border="0" alt="vlog_top" src="http://lh5.ggpht.com/-3gIt9Tnwi4Q/UDEan28E-gI/AAAAAAAAAaA/3UWBaOOojvA/vlog_top_thumb3.png?imgmax=800" width="345" height="237" /></a><a href="http://lh4.ggpht.com/-HOKvPGMlaE0/UDEao6_34AI/AAAAAAAAAaI/2LscxgvB2X4/s1600-h/vlog_blk4.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="vlog_blk" border="0" alt="vlog_blk" src="http://lh3.ggpht.com/-oJ3acb2Oolo/UDEaqJlRgbI/AAAAAAAAAaQ/emEcalbmcrM/vlog_blk_thumb2.png?imgmax=800" width="320" height="240" /></a></p> <p> </p> <p>Needless to say the hierarchy can be very deep and totally encrypted etc. It is all about tree traversal and printing the relevant portions of vpi_get as in:</p> <p>Following is a code snippet from the VPI/PLI C-code:</p> <p><a href="http://lh6.ggpht.com/-1qKiwAhNw5s/UDEarTEr3FI/AAAAAAAAAaY/KsDmlqWIuA0/s1600-h/vpi_c15.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="vpi_c" border="0" alt="vpi_c" src="http://lh4.ggpht.com/-CWnHOqVM0tE/UDEasqs06cI/AAAAAAAAAac/61RCTAaDoqQ/vpi_c_thumb13.png?imgmax=800" width="612" height="225" /></a> </p> <p> </p> <p>Now wrap that inside a tree walker code that would walkdown your Verilog hierarchy (post elaboration) such as:</p> <p> </p> <strong></strong> <p><a href="http://lh4.ggpht.com/-9vQa8hL1IY8/UDEatghom-I/AAAAAAAAAao/TSz8fDEhNFY/s1600-h/binary_tree_complete4.jpg"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="binary_tree_complete" border="0" alt="binary_tree_complete" src="http://lh6.ggpht.com/-qoihtSqH4gI/UDEavKmYDvI/AAAAAAAAAaw/eRYpqL-6LOQ/binary_tree_complete_thumb2.jpg?imgmax=800" width="497" height="302" /></a>   </p> <p> </p> <p>At each node, print the results.</p> <p><a href="http://lh6.ggpht.com/-hbXkICZqq6Q/UDEav-2F45I/AAAAAAAAAa4/bocBiHoe8Xc/s1600-h/results6.png"><img style="border-right-width: 0px; display: inline; border-top-width: 0px; border-bottom-width: 0px; border-left-width: 0px" title="results" border="0" alt="results" src="http://lh6.ggpht.com/-yt4bselHHHo/UDEaxftXDqI/AAAAAAAAAa8/dXROis3JqeY/results_thumb4.png?imgmax=800" width="611" height="169" /></a> </p> <p> </p> <p>Drop us a note in the comments below if you would like to see the complete VPI code listing!</p> <p> </p> <p>Who said Verilog is simple – it can become very interesting with large designs with interesting challenges!</p> <p>Now you see why <a href="http://ww.cvcblr.com" target="_blank">CVC</a> is in the best of Verification related technology when it comes to training engineers (freshers/experienced alike) – where else would engineers get to experiment and learn at their own pace all the way from UNIX, Verilog to SystemVerilog, Assertions, UVM and beyond? See <a href="http://www.cvcblr.com/trainings">http://www.cvcblr.com/trainings</a> for more!</p> <p></p> <p></p> <p></p> <p></p> <div style="padding-bottom: 0px; margin: 0px; padding-left: 0px; padding-right: 0px; display: inline; float: none; padding-top: 0px" id="scid:0767317B-992E-4b12-91E0-4F059A8CECA8:65f1c4db-edd8-4262-816d-0aab94692613" class="wlWriterEditableSmartContent">Technorati Tags: <a href="http://technorati.com/tags/Verilog" rel="tag">Verilog</a>,<a href="http://technorati.com/tags/EDA" rel="tag">EDA</a>,<a href="http://technorati.com/tags/PLI" rel="tag">PLI</a>,<a href="http://technorati.com/tags/VPI" rel="tag">VPI</a>,<a href="http://technorati.com/tags/hierarchy" rel="tag">hierarchy</a></div> CVC www.cvcblr.comhttp://www.blogger.com/profile/11394051247776533112noreply@blogger.com1