Wednesday, November 6, 2013

Asynchronous events and SVA – a quick primer

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During our recent SystemVerilog Assertions update webinar ( http://www.cvcblr.com/blog/?p=802 ) one of the audience raised a question on how...
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Wednesday, October 23, 2013

Catch-up with SVA 2009-2012 updates – free Webinar on Oct 31st

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Simplified Assertion Adoption with SystemVerilog 2012 (EU/ASIA) Date: Thursday, October 31st, 2013 Time: 2:00 PM-3:00 PM IST – India tim...
Sunday, April 21, 2013

Mind the GAP – even in SystemVerilog macro definition

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SystemVerilog enhances the TEXT-MACRO feature (a.k.a `define-s by many young engineers) of Verilog by a good length. Significant enhancement...
Friday, April 19, 2013

Smart constraint modeling in SystemVerilog

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With SystemVerilog language gaining popularity among user, it is getting interesting to see user asking similar/repeating “patterns” of chal...
Monday, April 1, 2013

SystemVerilog 2009 macro `__FILE__ – absolute or relative path?

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As many of our customer learn during our regular VSV training sessions , System Verilog added `__FILE__ & `__LINE__ macros similar to C...
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Friday, March 22, 2013

SV solver puzzle part II – “guidance” vs. “dictation”

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  With one of our recent blog entries on SystemVerilog constraint solver ( http://www.cvcblr.com/blog/?p=725 ) becoming so popular, severa...
Thursday, March 21, 2013

SVA: default disable – a boon or a bane?

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As the SVA usage expands/grows in the industry, so do the language syntax/features. One of the recent (2009) addition to System Verilog lang...
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