Free Seminar on "Quest for Scalable Verification => result:Questa + OVM "

Free Seminar on "Quest for Scalable Verification => result:Questa + OVM "

With ever growing complexities of ASICs (and FPGAs), the task of verifying them has become a “never-say-done” activity. Given the need for multiple levels of reuse in design and verification, a stand-still approach to verification doesn’t hold good any longer. It requires continuous inflow of new ideas, thoughts and technologies to address the complex requirements. Hence the quest for a scalable verification has been a continuous one. A series of innovative, path breaking technologies have emerged over the last decade to address the verification challenges. Back in 2005 IEEE standardized SystemVerilog as the standard HDVL to incorporate many of these technologies with a Verilog flavor. Since then SV has been making its way into being the most preferred language for ASIC Design and Verification across the globe. However leading edge semiconductor houses have quickly realized that using SystemVerilog on its own might lead to sub-optimal benefits especially in Verification. This is due to the fact that the language is vast and not every team has enough time to experiment with the right usage model for the task at hand. This is the primary motivation behind adopting a Verification Methodology - to get more productive in less time.

OVM as announced in late 2007/early 2008 is proving to be a very good choice for building such scalable verification infrastructure as it has all the classical methodology features plus some of the most advanced, proven verification techniques such as Virtual sequences, factories etc. The good thing about OVM is it is open, and there is a vibrant ecosystem building around OVM. We at CVC have an everlasting thirst to be on top of any new verification technology. As part of Mentor’s Questa Vanguard program, CVC has had the privilege of experiencing the power of OVM early with a robust, easy-to-use verification platform – Questa!

As with any new technology, the initial adoption requires some ramp up time. During our early engagements with building OVM compliant verification environments we went through a series of learning steps. As a result of it, we at CVC recently composed a step-by-step OVM quick start guide that we share with our customers. In this seminar, we share an early preview of this step-by-step guide with a simple packet de-serializer design. We walk through the following topics:

• SystemVerilog features for Verification
• OVM introduction
• DUV - Packet de-serializer
• Step-by-step OVM approach with code snippets
• Highlights of important Questa features that helped us in the process
• Results, summary and looking forward

To attend this seminar: Click on: Register for CVC OVM with Questa seminar. If the above link doesn’t work, send an email to mailto:cvc.training@gmail.com;?subject=CVC_OVM_Questa Please include the following details in your email.

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Venue: CVC Bangalore Office (Ground Floor)

Date: 2^nd Aug 2008, Saturday at 15.00 (3.00 PM)

Agenda: 1 hour presentation followed by a quick demo + Q&A

Bangalore, July 23rd: Free seminar on: Advanced Verification with Aldec’s Riviera-PRO - with SystemVerilog

Advanced Verification with Aldec’s Riviera-PRO

Given the ever growing complexities of SoC designs, the task of verifying these SoCs is herculean indeed! A series of innovative, path breaking technologies have emerged over the last decade to address the verification challenges. Industry is seeing a culmination of these techniques in the form of new languages such as IEEE 1850-PSL, IEEE 1666 SystemC etc. Every language provides a complementary strength, and addresses specific problem. Recently, many of these separate language capabilities have been integrated into single language and are available as IEEE-1800 standard SystemVerilog (SV). SV is poised to be the choice of DV engineers for many years to come due to the overwhelming support from all tools and the greater eco-system of trainings, books and papers.

Aldec has been the primary EDA provider for various ASIC and FPGA design tasks for 24 years by now. Riviera-PRO is a proven high-performance, mixed-language simulation engine with advanced debugging tools for ASIC and FPGA design teams. Riviera-PRO supports VHDL, Verilog®, SystemVerilog, SystemC, C/C++, PSL and OVA assertions from one common design environment. Riviera-PRO enables mixed RTL debugging, long regression testing, timing simulation and electronic system level (ESL) verification.

IEEE 1800, SystemVerilog is a major extension to Verilog-2001, adding significant new features to Verilog for verification, design and synthesis. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of a
complete Object-Oriented paradigm features. We at CVC have been on the top of leading edge verification technologies for the past half-a-decade. We recently setup an advanced verification environment for a memory controller using SystemVerilog and Aldec’s Riviera-PRO. In this seminar and share that anecdote with the attendees. We walk through the following topics:

· Advanced Verification techniques

· Verification Architecture for Memory controller

· Key SystemVerilog features used in this verification with code snippets

· Screenshots of important Riviera-PRO features that helped us in the process

To attend this seminar, confirm your registration by sending an email to cvc.training@noveldv.com , cvc.training@gmail.com with subject as CVC_Verif_Aldec Seminar. Please include the following details in your email.

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Official Email ID:
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Venue: CVC Office (Ground Floor)

Date: 23^rd July 2008 at 11.00 A.M
Agenda: 1 hour presentation on Advanced Verification Using Aldec followed by demo