Thursday, March 29, 2012

Working with default arguments in SystemVerilog & OVM hierarchy building

Recently Amit (Yet another successful VLSI engineer from CVC’s incubation, asked this:

In OVM/UVM ( I am little confused about the way components are hooked-up hierarchically. Consider the code below:


In the above constructor ,sometimes I am writing parent =null and some times only parent ,and then passing in;, blindly i am doing this ,but i am not understanding why i am making parent=null and sometime leaving this as parent . what will be the effect of making so. kindly help me.


As an enhancement to Verilog, System Verilog allows “default values” for function/task (methods) arguments. By doing so it allows the caller of these methods to have the flexibility in number of arguments – a.k.a variable arguments to a function (though not overloading as in VHDL). So in the example above, the new has 2 arguments, both having default values.

If we had: (NOTE: the 2nd argument has NO default value)



then the caller of this function must pass atleast 1 argument.


Summary: if a default value is provided in the function declaration, then while calling the function, that argument becomes “optional”.

Now what is the impact of this in OVM context? Actually quite a bit – it is about the “TB hierarchy” – a.k.a print_topology in OVM/UVM. See few screenshots from Aldec’s Riviera-Pro ( 2011.02 version below:

Consider a simple OVM based env with:

env –> agent –> monitor

If monitor is constructed with “parent” set to “this” (i.e. the agent), then we get:




If monitor is constructed with “parent” set to “null” then we get:




It gets little murkier with OVM’s factory playing an interim layer with create – but that’s left as an exercise for the readers :-)

We at CVC feel proud to support customers even long after their short training stay with us, see our list of training sessions at:

Happy SV-ing :-)


Monday, March 26, 2012

Using SystemVerilog Assertions to check clock inversion

A while ago, a user asked :

I am trying to check that one of the my inverse clk is reverse of sys_clk:

I have written assertions , but when I am seeing this its checking only on falling edge of sys clk !
Please advise
property me;
clk |-> ~clk_inverse;
inverse_pp: assert property (me)
$error ("inverse clk is not inverse as expected", $time);


Here comes the “deferred assertions” to your rescue – a new feature in SVA 2009 LRM.

ap_check_inv_clk : assert #0 (clk == !inv_clk);

Can be used both inside a procedural block (such as always_comb) or outisde (as a concurrent statement).


Try and let us know if it worked for you – BTW, don’t forget to turn SV 2009 flag ON to your SV tool to compile the above!

SystemVerilog OOP questions – interview or otherwise

As Indian VLSI industry is hiring at crazy rate for verification, SystemVerilog has emerged as a key differentiator in most of the front-end Verification job roles (see: With many engineers adding SV skills to their CVs – the interviewers are getting tougher and smarter in their questions during interviews. Some related to OOP are below, source:

As our CEO posted some code snippet to start with  -we thought we will assist our junior engineers to ponder around the same and explore more on this topic.

class base_pkt;
  bit b1;
  virtual function void display;
    $display ("base_pkt: b1: %b", this.b1);
  endfunction : display
endclass : base_pkt
class extended_pkt extends base_pkt;
  bit b2;
  virtual function void display;
    $display ("extended_pkt: b1: %b b2: %b", this.b1, this.b2);
  endfunction : display
  virtual function void ext_fn;
    $display ("EXT Function");
  endfunction : ext_fn
endclass : extended_pkt
class container_c;
  base_pkt b_p_0;
  function new;
    this.b_p_0 = new;
  endfunction : new
endclass : container_c
program test;
  container_c c_0;
  extended_pkt e_p_0;
  initial begin : b1
    c_0 = new;
    e_p_0 = new;
    c_0.b_p_0 = e_p_0;
  end : b1
endprogram : test

Some of the advanced questions from

    • can main access the methods and properties in the base_packet
    • can main access the new methods and properties in the extended_packet class as it is or any casting would be needed
    • assume one of the method in base_packet has a method that is virtual, what would happen if this method was called in the main method using the base class handle

Now – it is your turn to solve them based on above code starting point and ask more here in comments. We will try and help you with answers if you need!


Good Luck


Wednesday, March 14, 2012

Get started with VLSI at Engineering college – for free!


Here is a recent posting that TeamCVC did on Facebook group ( , thought it is worth sharing it widely. Bottomline – if you are interested in VLSI, there is nothing that stops you from doing it for free even at college level!


When you say "tools" - a full ASIC platform for free is not realistic, unless it is academic - in which case look at Alliance:

Though some of the tools in Alliance are industry ready, usually students in India have better tools at their disposal (just that they don't know about it). For instance:

Modelsim Student edition

Riviera-Pro student edition:

These tools will run on Windows and or Linux. One can install Cygwin ( and get Linux-like experience on Windows itself (to be ready for industry).

After you solve the tools puzzle, then comes "what to do with tools" - there are tons of projects you can contribute such as OVL

So once you decide to work on VLSI, there are ample opportunities to pick up. If you need further assistance feel free to visit us

Good Luck