Simplified Assertion Adoption with SystemVerilog 2012 (EU/ASIA)
Date: Thursday, October 31st, 2013
Time: 2:00 PM-3:00 PM IST – India time / 9:30 AM-10:30 AM CET (European time)
Host: Aldec, CVC’s valued EDA partner (www.aldec.com)
Presented by: Srinivasan Venkataramanan (http://www.linkedin.com/in/svenka3)
CVC (Contemporary Verification Consultants www.cvcblr.com) – Aldec’s Training Partner,
Assertions have been in use for over a decade for now, however, writing detailed, temporal expressions in plain SystemVerilog (SV) 2005 has been at times a demanding task for first time users. While it gets easier as users mature with SVA, the language has made it more straightforward to express complex temporals with recent additions to the standard.
With SV 2012 LRM becoming freely available to all users, the adoption is expected to grow much faster. This webinar will demonstrate some of the important LTL operators added to the SVA such as until, eventually, etc. Using real-life case studies, the presenter demonstrates how these new operators can significantly reduce complexity of SVA coding. Attendees will be taken through a small, real-life protocol and shown how to break down the requirements in an “edge-by-edge” approach to coding SVA. An Ethernet-like protocol case study will be used to demonstrate the value of assertions while building driver BFMs in UVM. This clearly highlights the benefit of adding assertions upfront in a project cycle by helping reduce the TB development time.
This is a FREE webinar, but registration is required. Choose your slot depending on your geography.
India/Asia/Europe: http://www.aldec.com/en/events/338
USA/Rest Of the World: http://www.aldec.com/en/events/339
