Fast-Track course on Verification Using SystemVerilog - Hyderabad
Quick facts
When: 13th /14th July (Sun/Mon)
Where: Hyderabad
Cost: Rs. 4000 /-
Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572
What’s SystemVerilog?
IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.
What’s a Fast-Track course?
A Fast-Track process is intended to cut short detailed explanations aimed at getting to the core of the subject ASAP. CVC’s Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.
Who should attend?
Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV in 1-day without bothering about the nitty-gritty in great detail.
What’s the cost?
The basic cost of this course is Rs. 4,000 /- + ST (12.36 %) per attendee.
Terms & Conditions
· In general we require that the fee is paid in 100% prior to the start of the training.
· For large corporate with more number of attendees to account for their internal process we do allow an exception to the above rule; however we charge an additional 25% of the training cost per attendee in such cases. In case the fee is paid after the training, the payment should be made within 1 week after the training is delivered. Any additional delay shall be charged at 10% every additional day.
· Any "offer" price mentioned in the course announcement is applicable only for individual attendees and not for corporate.
Cancellation Policy
Course tuition is fully refundable up to one week before the class starts. Cancellations within a week (2-7 days) of the class start date will incur a 50% cancellation fee. Those who cancel fewer than 2 days prior to the class will be billed for the full amount of the tuition. A no-show will be treated as cancellation and no refund shall be given. For genuine cases of absence, we can provide a training token that the trainee can avail in one of the future training classes subject to space availability.
How do I register for a class?
To attend this class, confirm your registration by sending an email to cvc.training@gmail.com. +91-9916176014, +91-80-41495572
Please include the following details in your email:
Name:
Company Name:
Official Email ID:
Contact Number:
Preferred Date: 13th or 14th July (Sunday or Monday)
Are there extended versions of these courses?
Of-course yes! Our flagship trainings on Verification Using SystemVerilog are originally designed for 3 variants:
· 10-day class with extensive labs and a complete project (suitable for students, jobseekers)
· 3-day class and
· 2-day class
So, depending on how much time you can invest, you pick the one appropriate to you. Needless to say – the more time you invest, the better you master this amazingly powerful language.
Trainer Profile
Ajeetha Kumari, Design Verification Consultant· Has 8+ years of experience in Verification
· Co-authored leading books in the Verification domain.
· Presented papers, tutorials in various conferences, publications andavenues.
· Worked with all leading edge simulators and formal verification(Model Checking) tools.
· Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDVand OOP for Verification
· Holds M.S.E.E. from prestigious IIT, Madras.
Other Trainings:
- Comprehensive Functional Verification (CFV)
Languages
- IEEE 1800 SystemVerilog Design (SVD)
- IEEE 1800 SystemVerilog Assertions (SVA)
- IEEE 1800 SystemVerilog for Verification (SVTB)
- IEEE 1850 Property Specification Language (PSL)
- IEEE 1647, e-language
- IEEE 1364 Verilog
- IEEE 1076 VHDL
- IEEE 1800 - SV Based Verification Methodology Manual (VMM)
- IEEE 1800 - SV Based Open Verification Methodology (OVM)
- Assertion Based Verification (ABV)
- Coverage Driven Verification (CDV)
- Gate Level Simulation
- ABV beyond RTL
- OOP Basics
3 comments:
Note sure about CVC's training content, but we didn't have a good experience trying to setup training with CVC. Firstly, we got different quotes for the same trainings. Both Ms. Ajeetha and Karthick didn't respond to our training needs like they promised. Ended up taking the training from Doulos.
@popeye - thanks for sharing your experience in public. For our content - we let our customers speak, see: http://www.cvcblr.com/blog/?p=200
On the pricing - you are quoting/commenting on a post that's 4 years old - back from 2008. And yes we have slightly different pricing for different customers - there are group discounts available. Corporate requirements tend to be different at times and we customize content accordingly, so cost may need to be tweaked. And we cater to fresh graduates too, who can't afford the same cost as Xilinx for instance.
There are other factors that determine the cost such as duration, weekday/weekend etc.
To draw a parallel - look at Xilinx FPGA costing - from various channels we do get slightly varying prices, this is very common.
Anyway, good you found an alternate. We look forward to next opportunity with you, perhaps in 2013!
We wish you a very happy new year 2013.
Srini
www.cvcblr.com/blog
design verification training
Design Verification course for just Rs.55000. Dial us on +919483440125 for registration procedure. Hurry up...Limited seats available.
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