An evening full of Do’s & Don’ts in OVM/UVM with Cliff Cummings

Clifford Cummings (http://www.linkedin.com/in/cliffcummings) is a crowd puller – no doubt. Consider:

• Hot summer mid-day (2 PM start time)
• Bangalore traffic/center of city (potential peak traffic towards end time of 5.30 PM)
• A venue known/infamous for a “HUGE” area but no so frequented by hi-tech community of Silicon Valley of India, past events over there had history of terrible attendance

Yet there were close to 70+ Verification engineers at Cliff’s UVM/OVM seminar aptly titled as:

“Advanced SystemVerilog Tips Including OVM & UVM Tips”

 

It was indeed for Advanced System Verilog users as he had most of the slides on OVM/UVM. TeamCVC (http://in.linkedin.com/in/cvcblr) specifically its trainees, some 11 of them were there cherishing their stint at CVC (www.cvcblr.com) as they hear a world-class seminar and being a fresh graduate, making sense out of that was  a pride on its own. That’s the power of CVC’s time proven EIC training (http://www.cvcblr.com/trng_profiles/CVC_EIC_profile.pdf) that takes in a fresh B.E/M.Tech graduate and turns them to be most sought out Verification engineer in local market.

Madhavi Rao of Cadence (http://in.linkedin.com/in/madhavirao) has done an excellent job in making the event popular and driving it to customers. TeamCVC did their bit, by blogging about it via: http://www.cvcblr.com/blog/?p=325 and also tweeted via: http://twitter.com/cvcblr – for those who believe (still) that Social Media is not engineers/hi-tech, there were more than 5 folks who told me at the event that they heard it via Tweets and they signed-in for the event!

Coming to the event technical content – A good detailed, 60-page write-up by Cliff is at: http://j.mp/gJegMP And for those who cherish/enjoy live-tweets, let’s not repeat all the hardwork TeamCVC had put in live-tweets during the event itself, see: http://twitter.com/cvcblr

The true success of the technical value was evident towards the end – during the High-Tea, almost every attendee had atleast one TIP to go home with (many with more than 1 obviously), I heard things like:

I would not use global_stop_request after run_test

I would not look at enable_stop_interrupt

etc.

Cliff cited JL Gray (http://www.linkedin.com/in/jlgray) for his interesting analogy of OVM’s TLM port-export to the famous Hollywood Blockbuster Avatar Movie. I am still looking for more details on that comparison as it wasn’t easy to catch that link during Cliff’s brief notes.

Cliff’s own explanation of port-export to a driving-a-car using steering-wheel was interesting as well.

Cliff’s session on handling end-of-test was the best pick in this event. Start with the following:

  initial begin : end_of_test_try

    run_test();

    global_stop_request;

  end : end_of_test_try

If you need more details, read: http://j.mp/gJegMP

It was indeed a nice evening with Cliff and other Verification geeks of Bangalore. Now, let’s look forward to how the Pune event goes, maybe http://twitter.com/punechips will provide us the live-tweets :-)

Spend 3 hours to know more about UVM, OVM with Cliff Cummings @ Bangalore/Pune

If you are curious about recently released UVM standard – you won’t have missed to note the DVCon-2011 blogs/tweets etc. Some of those captures can be seen at http://www.cvcblr.com/blog/?p=283 

http://www.cvcblr.com/blog/?p=298

http://www.cvcblr.com/blog/?p=322

Now, in case you didn’t visit DVCon, here is UVM coming to YOU – at Bangalore & Pune. Thanks to Cadence & QLogic, there are free UVM update events being scheduled on Apr 13th & Apr 19th. Register for free right away.

Agenda:

• New UVM 1.0 overview and comparison to OVM
• Important OVM and UVM phasing
• Secrets in mastering OVM and UVM
• Graceful termination of tests in OVM and UVM with emphasis on the objection mechanism
• Some of Cliff's favorite SystemVerilog tips and tricks
• Some early UVM techniques and best practices

Date	Time	Location
April 13, Wednesday	2.00pm – 5.30pm	Bangalore Auditorium 1 NIMHANS Convention Centre Hosur Road, Bangalore
April 19, Tuesday	4.00 – 7.30pm	Pune, MCCIA Auditorium A-Wing Ground Floor MCCIA Trade Towers (Building with Crossword Book Store) Senapati Bapat Road, Pune

Pune – the “Oxford of the East”, SystemVerilog and the vibrant community

Last week TeamCVC held a 4-day training on System Verilog at Pune – a pleasant city in the western ghats of India, also known as the "Oxford of the East" due to its vast student community & research institutions.

TeamCVC has been to Pune few years back for a VMM training, see some of those experiences at http://bit.ly/eHMaH7

But this visit has shown how fast this city has been growing and the recent boom it has been experiencing - atleast through an entrepreneur viewpoint. The first thing that struck me on my way to the hotel from airport was the flurry of developments – almost 90% of all hoarding/banners showing upcoming apartments, It is almost like Bangalore some 10 years back – with so many IT firms growing their staff strength, new office spaces being built etc.

The weather was pleasant, gets quite hot mid-day but then cool breeze in the evening, gets little cold during early mornings. Kind of similar to Bangalore, atleast for this period of the year.

The Hinjewadi area/IT park is amazingly clean, well maintained, with wide roads. Trafiic was sensible, a BIG sigh of relief for a Bangalorean :-) Though there are BPO vehicles plying along the roads, they are not as hars driving as their counterparts in Bangalore are.

Coming to the training folks, what really surprised me was the true cosmopolitan nature of the IT crowd there (from the general media projection of Maharashtra). There were folks from Andhra, Karnataka, Gujarat, Delhi and of-course Pune & around. The razor sharp audience kept the training truly interactive and alive. I generally have a higher image/perspective of Maharastrians when it comes to intellect and I wasn’t proven wrong, the audience were dot on time with labs, always had the enthusiasm for learning more – something that a passionate trainer would look forward to in each session. It is indeed a pleasure to have such attendees as connoisseur. It was a mix of few experienced folks and some fresh graduates, similar to our recent Cochin experience (Read: SystemVerilog Assertions Field-day). However, the biggest difference was that the attendees were finishing all labs on time and were asking for more stuff, pretty impressive talent pool indeed!

There were some good discussions around the SystemVerilog assertions – specifically on the Sequence repetition operators and the first_match. While we cover the basic repetition operators in our first session on sequences, we defer the first_match to advanced sequence session. One set of attendees finished the lab on sequences faster and started debate on "potential multiple matches" and the necessity of the consequent to hold for all matches. VCS DVE’s sequence debug/visualization came in very handy to appreciate the SVA behavior.

The discussion on $cast in SystemVerilog went on really nice, with new animation kicking in on demand and was well received. While the "syntax" was learnt the hard way, some folks weren't convinced on its real usage – not uncommon as the first level SystemVerilog course, we call it VSV () shows you how to use it, but our methodology sessions truly leverages it. Some of the tech-hungry attendees said "Yeah Dil Maange More.." and we quickly opened up $VCS_HOME/etc/rvm/vmm.sv and showed some of the real life usage of $cast – the instant reaction was "Oh My God – so common in reusable code.

Wanted to add more stuff, but realize it is already a long post, so perhaps some other time with few images to make it more interesting to read.

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