Last week TeamCVC held a 4-day training on System Verilog at Pune – a pleasant city in the western ghats of India, also known as the "Oxford of the East" due to its vast student community & research institutions.
TeamCVC has been to Pune few years back for a VMM training, see some of those experiences at http://bit.ly/eHMaH7
But this visit has shown how fast this city has been growing and the recent boom it has been experiencing - atleast through an entrepreneur viewpoint. The first thing that struck me on my way to the hotel from airport was the flurry of developments – almost 90% of all hoarding/banners showing upcoming apartments, It is almost like Bangalore some 10 years back – with so many IT firms growing their staff strength, new office spaces being built etc.
The weather was pleasant, gets quite hot mid-day but then cool breeze in the evening, gets little cold during early mornings. Kind of similar to Bangalore, atleast for this period of the year.
The Hinjewadi area/IT park is amazingly clean, well maintained, with wide roads. Trafiic was sensible, a BIG sigh of relief for a Bangalorean :-) Though there are BPO vehicles plying along the roads, they are not as hars driving as their counterparts in Bangalore are.
Coming to the training folks, what really surprised me was the true cosmopolitan nature of the IT crowd there (from the general media projection of Maharashtra). There were folks from Andhra, Karnataka, Gujarat, Delhi and of-course Pune & around. The razor sharp audience kept the training truly interactive and alive. I generally have a higher image/perspective of Maharastrians when it comes to intellect and I wasn’t proven wrong, the audience were dot on time with labs, always had the enthusiasm for learning more – something that a passionate trainer would look forward to in each session. It is indeed a pleasure to have such attendees as connoisseur. It was a mix of few experienced folks and some fresh graduates, similar to our recent Cochin experience (Read: SystemVerilog Assertions Field-day). However, the biggest difference was that the attendees were finishing all labs on time and were asking for more stuff, pretty impressive talent pool indeed!
There were some good discussions around the SystemVerilog assertions – specifically on the Sequence repetition operators and the first_match. While we cover the basic repetition operators in our first session on sequences, we defer the first_match to advanced sequence session. One set of attendees finished the lab on sequences faster and started debate on "potential multiple matches" and the necessity of the consequent to hold for all matches. VCS DVE’s sequence debug/visualization came in very handy to appreciate the SVA behavior.
The discussion on $cast in SystemVerilog went on really nice, with new animation kicking in on demand and was well received. While the "syntax" was learnt the hard way, some folks weren't convinced on its real usage – not uncommon as the first level SystemVerilog course, we call it VSV () shows you how to use it, but our methodology sessions truly leverages it. Some of the tech-hungry attendees said "Yeah Dil Maange More.." and we quickly opened up $VCS_HOME/etc/rvm/vmm.sv and showed some of the real life usage of $cast – the instant reaction was "Oh My God – so common in reusable code.
Wanted to add more stuff, but realize it is already a long post, so perhaps some other time with few images to make it more interesting to read.
Powered by Qumana
No comments:
Post a Comment