Automatic generation of checkers & coverage model – A NextOp 101

 

Earlier this week John’s DeepChip ran a user survey asking for “edgy” questions for DAC-12 “Troublemaker Panel”. Here is what those came out for NextOp were: http://www.deepchip.com/items/0504-05.html

>> Yunshan, what does NextOp do and why should users buy your tool?

I am amazed at how “basic” some of these “queries” are – aren’t they supposed to be “edgy”? Sure John is doing a great job in publishing “AS-IS”, so can’t blame him for this, it is rather the typical limitation of small start-up, especially in EDA being unable to broadcast its value to masses. Here is my attempt, being a partner, promoter of this technology and SystemVerilog in general.

Assume that you are tasked with a I2C IP/sub-system verification (it isn’t that uncommon, is it?). Consider an AMBA based SoC in which this I2C is being integrated, the other side of this IP is typically APB.

Your company has tight timelines for this and has provided you VIPs a la modern day UVC (UVM Verification Component). So your job is to simply hook-up those UVCs as shown below:

 

Assuming the UVCs live up to their promise of plug-n-play by your VIP vendor, this would be a 1 or 2 days job isn’t it? Then add few more days to tighten the “scenarios”, then you are done in a week, right?

So a typical I2C verification project should be atmost 1 week project, Huh? Is life really that simple? Of-course not! – this is where NextOp plugs-in. UVM is great, and hopefully the maturing VIP industry around it can indeed provide you solid plug-n-play-able VIPs for you. This does automate majority of “stimulus” creation and some of “protocol checkers” and “functional coverage”. But what about “your design specific” checkers & coverage? Isn’t that the MOST important and hence is the reason why you are tasked with this project to start with?

So how do automate the “design specific” checkers & coverage? This is how – a NextOp 101 starts here.

 

 

You run the UVCs + RTL design as-is (after that 1 week of your project start, let’s say). Include 2 simple PLI calls:

$himafile & $himavars

This flow would eventually create a set of “properties” or “observations” that your TB + RTL is showing up during the regressions as a simple, plain English TEXT file. No, it is not a syntatically “overloaded/crowded” SVA/PSL code for your “kind review”, rather simple format such as (BTW, the below screenshot is from a  different, DDR design, just got lazy enough not to do that on that specific design):

 

Now you sit with your designers and classify them as “assertions” and “coverage holes”. Typically the designer spends 2-5 minutes per-property to decide this classification. Then you run another “utility” called “hima” that spits out SVA/PSL/OVL/Verilog assertions for you to add to your UVM bench during next random regression.

It is quite common that users identify bugs/coverage holes during the review itself than waiting for next runs!

Now quoting a reader’s question from that Jonh’s “edgy questions” (I do agree this is an “edgy question”)

 Why should we pay extra for BugScope when we can get SNPS/CDNS/MENT
  formal verification tools for "free" (or at a heavy discount) as
  part of a bundled deal?

 

Hopefully this blog entry answered it atleast partially – it is NOT available as part of any other EDA vendor as of today!

Yes, you do pay extra – bu then YOU-GET-WHAT-YOU-PAY-FOR :-)

Enjoy the ABV with NextOp!

Technorati Tags: SystemVerilog,EDA,NextOp,Assertions,checkers,coverage

What’s new in Verification 2012? Pre-DAC 2012 analysis of exciting EDA solutions

With DAC around the corner, it is time to update our readers on what’s new in Verification in 2012 from EDA perspective. Here is what our TeamCVC have found so far as interesting, will be glad to add more if you drop us a note via info@cvcblr.com or as comments here in this blog itself!

Here is an alphabetical order of various vendors & their solutions.

AgniSys – your neighborhood automation solution for registers & more

If your design is all about IPs and sub-systems with say,more than 50 registers – you would be using one of the several formats (standard/proprietary) to define, maintain and manage the ever changing fields/blocks etc. If you have to manually code these registers in SystemVerilog/VMM/OVM/UVM/eRM – you know how hard it is, how laborious it is and how many hours it consumes to keep them upto-date. This is precisely where AgniSys fits into your flow. Basically their IDesignSpec is a plug-in to Word/XL/FrameMaker etc. to create register specification in various formats of your choice. Here is what it can do (picture below):

If you thought it can only be for Verification team, be ready for more: it generates:

• RTL code (for Reg RD/WR)
• C-headers for SW team
• UVM/VMM/OVM code for Verif teams
• Assertions
• Functional coverage etc.

All this and more for almost free – Yes indeed! They now offer a free version of their popular IDS for even “commercial use” – see: http://www.agnisys.com/products/66-idsfree 

Aldec’s Riviera-Pro brings UVM, OVM & VMM to desktop & on Cloud!

If you thought all the buzz around SystemVerilog, VMM/OVM/UVM is all for ASIC folks on Linux alone, be ready for some pleasant surprise! Aldec with its much praised easy-to-use tools like Active-HDL, ALINT etc. has built Riviera-Pro to bring these technologies to your laptops/desktops under Windows (and Linux of-course). Their intuitive debug and code-entry features are now available for SystemVerilog/UVM too. Do visit them at their booth or register via:http://www.aldec.com/en/events/sessions/38 to learn more about their debug features such as Transaction Recording, message displays etc.

Also they recently introduced Aldec Cloud – perhaps a bold step towards UVM on cloud!

 

Checkout their free trial @ http://www.aldec.com/en/solutions/functional_verification/aldec_cloud

Axiom’s MPSim & DesignerUVM – the latest in UVM tools!

If you were following the availability of multi-threaded simulators in the market, it is quite possible that you had noticed the front runner in this space – the MPSim from Axiom.  MPSim was the very first one to address the multi-core simulations in EDA domain and since then have grown leaps and bounds to become a strong SystemVerilog simulator with all methodologies such as VMM/OVM and UVM. It also has low power features like UPF that makes it a very compelling product for ASIC houses with large simulation requirements. Axiom is known for performance, but not just that!. It is infact their added debug capability that makes them even more compelling alternative to other vendors. In this Video interview, Tarak from Axiom explains their new debug feature DesignerUVM. 

Quoting Tarak: “You can do lot of simulations, but ultimately the engineering productivity comes from the ability to debug designs”:

We couldn’t agree more! It is Debug that takes whole lot of time and it is quite unfortunate major EDA vendors have not focused their R&D energy on this as much as they perhaps should. Consider the following scenarios in UVM environments:

• A factory override didn’t occur/work as you expected it to
• get_config_string failed to fecth correct value
• In an array of virtual interfaces being hooked up to physical interfaces, something went wrong and you observe incorrect drives/samples
• Port-to-export connections seem wrong

Does your existing Debugger(s) assist you in finding this? (besides gvim/Emacs, find, grep etc.)? If not – it is time to wake up and yell for more from your vendor. Now they have a reason to listen to you – as otherwise YOU as a customer have an alternate – the Axiom DesignerUVM will do these for you!

Breker Systems – SoC level verification

Breker with its new TrekSoC is one of the hottest EDA solutions to watch for – given the huge increase in number of System-On-Chips (SoC) being designed/integrated. Ask yourself:

• How long can you continue with manually written C-tests?
• How long can you maintain 2 (or more) test-env
  • One for Transaction/UVM based and
  • Another for the actual processor RTL based, that require C-tests?
• What about multi-threaded tests? Can we even write them by hand and synchronize?
• Won’t it be nice to have a “single source” for both TXN tests & C-tests?
• Can we truly “reuse” knowledge from IP DITL (Day In The Life) to SoC?
• Can we quickly reproduce SoC level issues at IP level with know extra effort?

These are just some of the “tip-of-the-iceberg” problems of SoC level verification that Breker is attempting to solve for you! For sure you don’t want to miss this – if you are in SoC world (who isn’t BTW?)

Cadence’s AVIP – Accelerated VIP, next form of “Synthesizable VIP”?

For quite a while the industry has been talking about “Synthesizable VIPs” for the want of putting them into FPGAs/Emulators and get more cycles out of DV tasks. VMM started it with VMM-HAL, then came the flurry of Virtual prototypes/platforms that promise to allow smooth integration of various abstraction models in a simulation/emulation env. Cadence’s recent announcement on AVIP is worth noting in this space, see them at DAC for more.

Mentor’s UVM Express, UVMConnect & more..

Mentor recently announced their extended UVM initiatives via UVM Express & UVM Connect:

Their Verification Academy initiative continues to be very popular among users, even non-Mentor customers. Hats off to Dave Rich for keeping the quality of discussions/responses very neutral and technical!

 

NextOp – Assertion Synthesis/Mesh generation

Whether you are doing IP level verification, sub-system or SoC – assertions are your friends – to detect bugs close to the source, apply formal search, indicate coverage holes etc. One of the biggest challenges in adopting them however is – who will write them? This ONE BIG Question has kept the ABV adoption way too slow for too long a period in the industry. But no longer..hopefully if your company can invest in right technology. NextOp with its patented “Assertion Synthesis” can provide you high quality properties:

Yunshan, CEO of NextOp will be in John’s Troublemaker panel, so be there to hear him or ask him live at DAC.

SparkEDA – Ignite your Verification

A quiet storm in the making, SparKEDA spearheaded by Alex Gnusin is creating some very interesting solutions. Its Panda Formal verifier claims simplicity all along. What we really liked on their demo to TeamCVC was their “ASTRA Wave” – an assertion & document creator straight from waveforms, see below for a screenshot. If it works as handy as it promises/claims – this is worth an addition to every Desktop indeed!

 

Specman is alive & kicking in 2012!

In quite contrast to the very many who believed that Specman & the e-language is dead – it is alive and kicking even well into 2012! See various views at DeepChip pages if you wish. But the ground reality from India and Europe is that there are millions of lines of e-code and more is being written as we speak – some by our own TeamCVC for local customers here who simply refuse to move away from the all powerful IEEE 1647 e-language. The eWG http://standards.ieee.org/develop/wg/eWG.html has recently finished its latest LRM updates (read: http://www.cvcblr.com/blog/?p=333). Cadence continues its updates to Specman with features like:

• Parallel compile
• Compiled mode debug
• Save-restore, reseed on the fly etc.

The latest ClubT was held in Israel in Mar 2012 and hopefully sometime soon in India as well!

Synopsys DAC updates

Since the recent nSys acquisition, Synopsys’s VIP portfolio has become very strong and one can expect more native UVM VIPs from them soon. For DAC 2012 specifically their AMS story sounds interesting: http://bit.ly/KYVIBj

On “Verification Luncheon” they plan to talk about SoC level verification. Sure they would showcase the performance improvements to VCS, but hopefully they will also demo their approach to the manual C-test creation monster soon!

UVM 1.1b is almost there

Most of you are following the UVM development at Accellera and DAC is a great time to release a high quality version of ever growing UVM code base. Learn more about what’s new, and what’s lined up for UVM 1.2 etc. at: http://www.accellera.org/downloads/standards/uvm

What about UVM-like for VHDL users?

If you are a VHDL user and have been feeling let down by the marketing bigwigs of EDA vendors – don’t worry, here is OS-VVM for you: Originating from VHDL guru Jim Lewis through his several years of experience, OS-VMM provides:

• Constrained Random generation
• Coverage Model capturing

all in native VHDL. Add this to the most powerful temporal languages available for hardware design industry – the IEEE 1850 PSL – it is a great compelling solution for VHDL users indeed. BTW – if you didn’t know, VHDL 2008 version already incorporates PSL into it, so you just a VHDL license with your EDA tool to run ABV, CRV & CDV (unlike the relatively expensive SystemVerilog solutions), learn more at: http://www.cvcblr.com/blog/?p=436 

Other interesting ones:

Here are some of the other ones you might be interested in:

• EVE – its ZeBu is making more news
• Blue Pearl  -relatively new entrant made some noise about generating SDC/Constraints etc.
• Xilinx’s new Vivado is in the news for its latest SystemVerilog additions and all new ISIM simulator. It is yet to be seen how much UVM support they will add in ISM in years to come.
• RealIntent’s X-finder is another niche point tool that some of you may like!
• UVM Linter from AMIQ

 

Technorati Tags: EDA,Specman,SystemVerilog,DAC

A fairy tale on SystemVerilog MDAs and UVM field macros

 

In one of the semiconductor conferences, Dr. Satya Gupta http://bit.ly/KlQpxr mentioned on a lighter note that the Semiconductor/VLSI needs to be promoted more among young Indian engineers and need to be made more “attractive”. (Guess it was Mentor’s U-2-U in 2010, anyone?) – few of the panelists and audience threw out ideas on how to do the same – via contests, TV shows etc. Taking it little more seriously and using social media we at CVC (www.cvcblr.com) believe our blogs/tweets & Facebook updates are doing exactly that.

Here is a “fairy tale” on how SystemVerilog MDAs work (or not work) with UVM field macros. Consider that we have a 3-D array (2 unpacked dimensions and 1 packed dimension) as shown below (“mda_3d” in s2p_xactn below):

While it sounds simple enough, the devil lies in “detail”. When you need to copy/clone/compare you need to ensure this mda_3d is included just like other fields. Huh? That’s what UVM supports via “field_macros” isn’t it? How about:

 

Oh my dear! Hold your breadth – this works for scalar types, and for 1-D arrays but NOT beyond :-( . Since System Verilog supports “arbitrary” dimensions in MDAs (Multi-Dimensional Arrays), the UVM base class doesn’t provide macros beyond 1-D arrays. Bummer, so what’s next? Here is your helpline – the uvm_object::do_copy.

Here is a simple code snippet that augments the built-in automated “copy” routine to include user defined MDA such as our “mda_3d”.

 

 

With that – UVM has once again proven that while it is not obvious why it has so many hidden “gems” – they are all useful on a case-to-case basis. In Hindi we say “Har eak cheez zaroori hota hai”. As the popular AirTel advertisement goes (India specific, for International readers, see: AirTel commercial ad). In case you can related your facebook friends to UVM “features/functions/base classes” and wonder “How come I have so many friends” – as the ad says “Every friend is useful”

 

 

Happy UVM-ing.

TeamCVC

Technorati Tags: SystemVerilog,UVM

CRV, CDV & ABV for VHDL users – all native

If you have been in the ASIC/FPGA industry for the past 5 years or so, it is highly unlikely that you haven’t heard of these buzz words:

• ABV – Assertion Based Verification
• CRV – Constrained Random Verification
• CDV – Coverage Driven Verification

While many ASIC teams have started using these in mainstream, FPGA users are still catching up with theses. One of the primary reasons has been that many FPGA designers use VHDL for RTL and Testench traditionally. (Though there are some high end Verilog users too, let’s talk about them in a separate blog. Meanwhile those folks can see how to adopt System Verilog for FPGAs from: http://slidesha.re/KtLlFu )

While these modern verification technologies are language independent, there is an impression in the industry that they are provided only via SystemVerilog and is thus restricted for Verilog/SV users. Some VHDL RTL teams have been forced to migrate to SystemVerilog just for this purpose – frankly speaking, a die-hard VHDL fan wouldn’t like it and also for teams using VHDL for long it is way too hard to do this migration in short timeframe. More important question is – do I need to migrate to adopt these technologies? – The answer is technically NO. VHDL has been very strong in “adaptability” to various requirements and stood strong amidst tough competition. Its rich features such as overloading, encapsulation (via packages), configurations, data structures etc. have been exploited by various applications such as: modeling, RTL design, testbenches etc.

Assertion Based Verification in VHDL

 

Recently temporal assertions capability has been added to native VHDL from IEEE 1850-PSL and hence the new VHDL 2009 standard has full fledged temporal expressiveness natively. See a PSL tutorial @ http://www.project-veripage.com/psl_tutorial_1.php

Constrained Random Verification

Given the complexity of designs being done using VHDL and FPGAs it is becoming increasingly difficult to rely just on directed stimulus. Constrained random generation allows exploring newer paths in every simulation run.

VHDL with its package capability allows building constrained random generation feature natively into the language without much hassle. Recently released OS-VMM infact provides it off-the-shelf. See: http://osvvm.org/archives/category/randomization

Coverage Driven Verification

Coverage as a metric to measure verification progress has been around for decades in verification. Code coverage has been widely used by RTL teams. Recently Assertions via PSL-VHDL provide temporal coverage and can be very handy to capture functional coverage of control oriented features. For data oriented features, coverpoint, cross etc. can be created in VHDL via packages. And OS-VMM does exactly that for all VHDL users. See: http://osvvm.org/archives/339

 

In summary – all the modern verification technologies are now available to VHDL users natively – without any additional cost (of a mixed language simulator for instance). The OS-VVM is a great starting point for coverage & constraints and PSL-VHDL provides all the temporal capabilities. Start doing better verification in VHDL with: http://www.osvvm.org