Smart constraint modeling in SystemVerilog

With SystemVerilog language gaining popularity among user, it is getting interesting to see user asking similar/repeating “patterns” of challenges in various forums. One of them is on constraint modeling when it becomes more than simple “a > 10” like stuff. Recently a VerifAcademy user asked:

 

in my testbench i have to make a random signal "[31:0] distortion". it must contain one (or, in other case, two) hot bit(s) (hot bit is "1", all others are "0"). So i have a problem with writing a constraint: i really don't want to write all possible combinations of these bits (if there are two of them, there will be 32! combinations, so...). Does anyone have solution for this problem?

 

A smart model is indeed available via 2 features of this vast language – System Verilog:

1. A handy system function to count the number of “ones”

2. Constraints can use functions in expressions.

Combining the above two, here is a full solution to the above problem along with a sample run from Questa 10.2

 

Hope you enjoy the concise solution. Do call us via +91-9620209226 or training@cvcblr.com for learning more about this wonderful language and its applicability for your verification projects.

TeamCVC

 

 

Technorati Tags: systemVerilog,EDA

I know SystemVerilog, why bother me with UVM?

If you are a verification engineer in ASIC/FPGA domain, chances are very little that you have not heard of SystemVerilog. For the last 6+ years it has been making positive impacts to design and verification teams across digital design space.

Given this fact, this is no surprise there are several young engineers who jumped on to the bandwagon and picked up the language to a certain level. Many successful engineers in this part of the world have taken CVC’s VSV course as a wise step towards the same.

However when it comes to the production use, plain System Verilog falls behind in certain key areas. Make no mistake, it is a powerful language and is becoming even more powerful with the upcoming 2012 update. See our blog for more on those updates: www.cvcblr.com/blog

Many users ask us – why do I need UVM on top of SystemVerilog. While there are ample number of marketing material available on the net for free on this, here is a humble, technical attempt to challenge a solid DV engineer with decent SV skills.

Consider a simple Deserializer design: call it S2P (Serial-2-Parallel converter). It captures the input serial stream from start-to-end and sends out as parallel data at its output every 8 clocks. A typical waveform would look as below:

Now, let’s say that you are SV aware to the extent that you can comfortably create a verification environment in say 1 or 2 hours for this simple design.

Now let’s try and do “verification” – add a negative test – i.e. create a scenario in which:

• There are ser_sop with NO ser_eop in between

See a sample screenshot below:

Remember, it is a negative test and hence you are NOT allowed to change any existing code. Can you achieve this in plain SystemVerilog without UVM?

If the answer is simple YES, we would love to hear your solution (add via comments here, below). No, don’t think of tricks like “force/release” etc. Attempt it as a pure SystemVerilog coding exercise.

The reality is – of-course we can, if we architect it upfront with factory and/or callback. That’s kind of what a framework such as UVM does for you. So UVM is nothing but 100% SystemVerilog, but wrapped in with a series of base-classes, built-in features that make your ‘verification” easy.

Join us for our upcoming UVM training session to know more on this challenge.

Bottomline – UVM is made to make your verification task easier, though it achieves it through a myriad of base classes. Luckily, users need to bother with only about half-a-dozen of them or maybe 10. But that’s only if you are educated well on UVM and trained by experts. If not, chances are you will loose yourself in the UVM base-class maze trying to make a decent way-out! Choice is yours!

Technorati Tags: SystemVerilog,EDA,UVM

Bringing in uniqueness constraint to SystemVerilog – welcome P1800-2012

If you are involved in functional verification I am sure you have atleast heard of System Verilog as the IEEE standard. The first IEEE standard was released back in 2005 and went in for a revision during 2009. Now there is yet another major update – 2012, expected to be fully ratified by early 2013 (on time for DVCon 2013). Here is a nice blog on this: http://blogs.mentor.com/verificationhorizons/blog/tag/ben-cohen/

A major part of this new version is all about assertions/SVA. If you need a detailed list of changes and examples, with applications – look no further, get hold of our new SVA 3rd edition @ SVA book 3rd edition @Amazon

In this article I wanted to introduce another nice, tiny, handy feature – unique constraint in SV. To give a background, consider a classical crossbar switch:

 

While every CPU can talk to/access every memory, for every access uniqueness must be maintained in terms of one-to-one connection. This is usually referred to as “Uniqueness Constraint” (ref: http://www.wonko.info/ipt/iis/infosys/infosys5.htm). In SV 2012, with unique constraint feature one may code a transaction model for this as:

 

 

One could perhaps combine this with a foreach and make it more elegant etc. But the bottomline – the unique constraint is really handy at times!

Welcome SV 2012/2013 :-)

Now our training in VSV (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) can cover this as a lab exercise – make sure you enroll in a session to learn more! See: http://www.cvcblr.com/trainings for more!

Technorati Tags: SystemVerilog,EDA

Help yourself & UVM community by sparing few minutes – Verilab’s UVM survey

 

UVM Runtime Phasing and Phase Jumping Survey

If you are well aware of UVM runtime phasing/phase jumping issues, quickly help yourself and the UVM community at large by filling out this survey:

• Verilab UVM Phasing Survey

Now for a background and for those who are “undecided” whether or not I have an issue with it, here is more information:

One of the significant updates done to OVM while bringing up UVM as the standard for verification methodology was the phasing. (For a detailed paper on user issues with OVM phasing approach, see: http://www.synopsys.com/community/snug/india/pages/abstracts.aspx?loc=india&locy=2011 and https://www.synopsys.com/news/pubs/snug/india2011/TA1.2_Intel_paper.pdf)

As with any standard development, there are differing view points coming from various experts, users etc. around the globe.India being the most vibrant Verification geography, it is very probable that many of the verification leads here face these problems day-in and day-out. So why not speak up and help us fix the UVM phasing the way YOU would like it?

Verilab, a premier verification consulting firm based in the US is conducting a survey to find out whether UVM users are currently taking advantage of runtime phasing and phase jumps, and if so, whether or not they would be impacted by certain changes the committee might propose.

So in case you are an active user of UVM, please spare a few minutes and take the survey at:

• Verilab UVM Phasing Survey

Technorati Tags: UVM,EDA,VIP

Reducing power in a smartphone – who-will-bell-the-cat? – Possible answers from ARM

Earlier this week, Simon Segars, EVP & GM Processor and Physical IP Divisions (http://linkd.in/ThbmbZ) presented an excellent keynote at an invite-only, executive dinner event around the CDNLive India 2012 http://bit.ly/TxallC organized by Cadence. Our CTO Srini (http://linkd.in/e6cSbd)

His theme was around the low power requirements in modern mobile devices (understandably, as the market needs this topic and who is in a better position than ARM can talk about this – being at the center of most of those smartphones!)

In a well drafted, upto-the-point, picture-centric presentation Simon did a great job of explaining what ARM’s big.LIITLE architecture is all about!

As of today, ARM provides Cortex A-15 like cores for the high-end devices:

 

Quickly ARM realized there is a strong need for low-energy, low-cost cores too to serve the entry level smartphones – here comes the ARM Cortex A-7

 

Now with lot of data mining and analysis Simon showed a typical pattern that revealed 2 important data points:

1. For a whopping 88% of the time in a day, the kind of applications that are run on a smartphone can be done using a processor with speed < 500 MHz
2. For the remaining 12% the frequency needs to be > 500 MHz – these are the videos, gaming etc.

Agreed, your numbers may vary, but the fundamental point is – one could do lot of power saving if we have a big processor to serve the high-end apps and a LITTLE processor to attend to the regular, most-of-the-day work such as MP3 playback, phone calls etc.And this is precisely what ARM’s big.LITTLE architecture is all about – have dual cores with Cortex A-7 & Cortex A-15. I found a slightly older slide on a quick Google search as below (Simon had an updated version of the same)

 

Now of-course you need multiple teams to take advantage of such an architecture to deliver low power promise to the end user. Simon showed a nice slide listing some of the key stakeholder/steps:

• The system architects to decide which app will run on which core
• The underlying OS to be able to support such a live-scheduling
• The design team to design and implement the various low power techniques such as the DVFS
• The all the more important DV team doing the functional Verification to ensure all the valid power state scenarios are working fine
• Backend team to implement the intended power-save architecture in layout
• Circuit designers to do their bit in choosing various low level power saving techniques

Now going back to our starting question of “Who-will-bell-the-cat” of that “magical low power smartphone chip” – Simon concluded it is ALL-of-us together who need to do this – can’t achieve this level of gains without collaboration!

We at CVC are doing our part of the ecosystem work by developing advanced low power verification training on UPF, CPF modeling, case studies on a UVM SoC Kit etc. So if you are in need of verification training on any of these topics, call us via +91-80-42134156 or training@cvcblr.com

 

Technorati Tags: Low Power,EDA,ARM,Cortex,UPF,CPF,UVM

Visualizing SystemVerilog event regions

One of the strengths of assertions in SystemVerilog is its well defined sampling semantics. Though it works out-of-the-box and is robust, many users don’t seem to understand it in depth. As we have been blogging on assertions – one needs to be very “pedantic”, i.e. detail oriented to be able to appreciate it, demonstrate it and understand it.

We at TeamCVC have been pioneering assertions as a focus area since our PSL book days (end of 2003, http://www.systemverilog.us/psl_info.html) and it has been almost a decade by now! We cover this in all our training sessions on assertions such as:

• SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf
• PSL: http://www.cvcblr.com/trng_profiles/CVC_LG_PSL_profile.pdf

Even during our popular VSV course (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) we touch upon this topic during the program block discussion. Below is an extract from our training/book on SVA (http://www.systemverilog.us/sva_info.html):

 

 

While the above slide goes well into the depth of this topic, often users ask us if they could “visualize it” inside waveform. Recently we did a SVA class for a VHDL customer who use Questa. Being part of QVP http://www.mentor.com/products/fv/partners/qvp we at CVC have access to Mentor’s latest technologies and this customer insisted that we use Questa during the labs. We enabled more debug sessions including their famous Questa ATV (Assertion Thread Viewer) feature. One of the nice examples our TeamCVC have created explains the events/time-regions nicely. See below for a screenshot:

 

It is almost the same as SystemVerilog LRM’s event Queue – brought inside the waveform, isn’t it! Here is a code snippet for the RTL regions such as “ACTIVE, INACTIVE & NBA” – this is same as in plain Verilog BTW:

 

Now recall that in testbench with System Verilog there is a program block that executes in REACTIVE region. And so are the assertion action-blocks. And within program block one can do blocking, #0 and NBA ssigns. So how does that get scheduled?

 

And relevant code-snippet for the REACTIVE assignments:

 

 

Putting the full waveform:

 

NOTE: the “time” doesn’t advance, it is only the DELTAs – Questa is powerful indeed in visualizing it, we will try and add other tool screenshots in near future if there is enough demand from you – our beloved readers!

Before we close, here is what a full, IDE (Integrated Development Environment) that Questa provides for this:

Hope you enjoyed this “flow of events” and the power of “visualizing” it – as much as we did. Drop your comments below!

Signing off with confidence, it is TeamCVC!

Technorati Tags: SVA,SystemVerilog Verilog EDA,Verilog,EDA,Questa,Debug

CVC announces new solutions around UVM for greater productivity – UnleashingUVM™

 

CVC to highlight UVM training, methodology consulting, auditing & debug capabilities at SNUG India Designer Community Expo

Bangalore, India, June 13, 2012 – CVC Pvt. Ltd., provider of the industry’s most advanced functional verification training solutions, today announced that it will be participating in the Synopsys Users Group (SNUG) Designer Community Expo (DCE) Wednesday, June 13, booth #200 in the IC Verification community. UnleashingUVM™ is CVC’s series of solutions centered around Universal Verification Methodology (UVM). It brings in range of training tailored to different end-users such as IP verification environment developers, VIP users and SoC integrators. It also comprises of UVM debug utilities, UVM rules/guidelines, a comprehensive auditing for UVM compliance leading to higher verification quality.

The SNUG Designer Community Expo (DCE) is a unique networking event featuring Synopsys and its ecosystem partners from across the electronics industry. At SNUG DCE, Synopsys users can interact with exhibitors and see the latest design enablement solutions spanning seven Designer Communities: Compute and Design Infrastructure, Custom Design and AMS Verification, FPGA, IC Design, IC Verification, IP, and System-Level Design. CVC will be exhibiting in the IC Verification community.

Over the last 8 years, CVC has been working very closely with semiconductor design houses in India to assist them in deploying modern verification technologies such as SystemVerilog, SVA, VMM, RAL and UVM.

“We spoke to several customers and we heard different requirements. While some want very advanced UVM, pushing it even beyond the current base classes, others are using traditional HDL-based solutions, looking to move up to UVM in a phased manner,” said Ms. Ajeetha Kumari, CEO & MD of CVC Pvt. Ltd. “This led us to package several solutions under the umbrella of UnleashingUVM™ over the last few years,” she said.

 

Srinivasan Venkataramanan, CTO of CVC Pvt. Ltd further elaborated: “We assist customers to learn UVM all the way from basic SystemVerilog, as needed by the individual teams. We also offer various migration consulting and training for existing users such as OVM-to-UVM, VMM-to-UVM. Our key differentiator is our ability to quickly customize these solutions as per individual team requirements. Under UnleashingUVM™, we consult with customers on various UVM architectures such as advanced TLM connections to handle layered protocols. We also offer auditing of verification environments for UVM compliance and help customers to effectively debug complex issues such as objection hangs, timeouts and more.”

 

About SNUG

The Synopsys® Users Group (SNUG) was established in 1990 to provide users of Synopsys design tools and technology with an open forum in which they could exchange ideas, discuss problems and explore solutions. SNUG has emerged as the largest community of design engineers in the world, with 13 SNUG conferences worldwide drawing more than 9,000 Synopsys customers each year. Attendees represent the world’s largest semiconductor design and manufacturing companies as well as many innovative start-ups. At the heart of each SNUG event is a technical conference focusing on real-world design challenges and featuring peer-reviewed user papers, along with presentations from top Synopsys technologists and industry experts.

SNUG and the Designer Community Expo at SNUG are by-invitation events only for Synopsys customers. For more information, visit the SNUG DCE web page at: http://www.synopsys.com/Community/SNUG/India/Pages/DCE.aspx

About CVC

Contemporary Verification Consultants Private Ltd. (CVC Pvt Ltd.) is a VLSI ecosystem company based in Bangalore, India. We bring emerging technologies to end-users through our continued investment in latest technologies around functional verification. We achieve this vision through our training sessions; consulting on verification architectures, thorough design-verification reviews etc. For more information please visit www.cvcblr.com

 

UnleashingUVM™ is a trademark of CVC Pvt. Ltd.

All other trademarks are the property of their respective owners.

For more information, contact:

Srinivasan Venkataramanan

srini@cvcblr.com

Technorati Tags: UVM,SystemVerilog,VMM,OVM,EDA,Debug

Automatic generation of checkers & coverage model – A NextOp 101

 

Earlier this week John’s DeepChip ran a user survey asking for “edgy” questions for DAC-12 “Troublemaker Panel”. Here is what those came out for NextOp were: http://www.deepchip.com/items/0504-05.html

>> Yunshan, what does NextOp do and why should users buy your tool?

I am amazed at how “basic” some of these “queries” are – aren’t they supposed to be “edgy”? Sure John is doing a great job in publishing “AS-IS”, so can’t blame him for this, it is rather the typical limitation of small start-up, especially in EDA being unable to broadcast its value to masses. Here is my attempt, being a partner, promoter of this technology and SystemVerilog in general.

Assume that you are tasked with a I2C IP/sub-system verification (it isn’t that uncommon, is it?). Consider an AMBA based SoC in which this I2C is being integrated, the other side of this IP is typically APB.

Your company has tight timelines for this and has provided you VIPs a la modern day UVC (UVM Verification Component). So your job is to simply hook-up those UVCs as shown below:

 

Assuming the UVCs live up to their promise of plug-n-play by your VIP vendor, this would be a 1 or 2 days job isn’t it? Then add few more days to tighten the “scenarios”, then you are done in a week, right?

So a typical I2C verification project should be atmost 1 week project, Huh? Is life really that simple? Of-course not! – this is where NextOp plugs-in. UVM is great, and hopefully the maturing VIP industry around it can indeed provide you solid plug-n-play-able VIPs for you. This does automate majority of “stimulus” creation and some of “protocol checkers” and “functional coverage”. But what about “your design specific” checkers & coverage? Isn’t that the MOST important and hence is the reason why you are tasked with this project to start with?

So how do automate the “design specific” checkers & coverage? This is how – a NextOp 101 starts here.

 

 

You run the UVCs + RTL design as-is (after that 1 week of your project start, let’s say). Include 2 simple PLI calls:

$himafile & $himavars

This flow would eventually create a set of “properties” or “observations” that your TB + RTL is showing up during the regressions as a simple, plain English TEXT file. No, it is not a syntatically “overloaded/crowded” SVA/PSL code for your “kind review”, rather simple format such as (BTW, the below screenshot is from a  different, DDR design, just got lazy enough not to do that on that specific design):

 

Now you sit with your designers and classify them as “assertions” and “coverage holes”. Typically the designer spends 2-5 minutes per-property to decide this classification. Then you run another “utility” called “hima” that spits out SVA/PSL/OVL/Verilog assertions for you to add to your UVM bench during next random regression.

It is quite common that users identify bugs/coverage holes during the review itself than waiting for next runs!

Now quoting a reader’s question from that Jonh’s “edgy questions” (I do agree this is an “edgy question”)

 Why should we pay extra for BugScope when we can get SNPS/CDNS/MENT
  formal verification tools for "free" (or at a heavy discount) as
  part of a bundled deal?

 

Hopefully this blog entry answered it atleast partially – it is NOT available as part of any other EDA vendor as of today!

Yes, you do pay extra – bu then YOU-GET-WHAT-YOU-PAY-FOR :-)

Enjoy the ABV with NextOp!

Technorati Tags: SystemVerilog,EDA,NextOp,Assertions,checkers,coverage

What’s new in Verification 2012? Pre-DAC 2012 analysis of exciting EDA solutions

With DAC around the corner, it is time to update our readers on what’s new in Verification in 2012 from EDA perspective. Here is what our TeamCVC have found so far as interesting, will be glad to add more if you drop us a note via info@cvcblr.com or as comments here in this blog itself!

Here is an alphabetical order of various vendors & their solutions.

AgniSys – your neighborhood automation solution for registers & more

If your design is all about IPs and sub-systems with say,more than 50 registers – you would be using one of the several formats (standard/proprietary) to define, maintain and manage the ever changing fields/blocks etc. If you have to manually code these registers in SystemVerilog/VMM/OVM/UVM/eRM – you know how hard it is, how laborious it is and how many hours it consumes to keep them upto-date. This is precisely where AgniSys fits into your flow. Basically their IDesignSpec is a plug-in to Word/XL/FrameMaker etc. to create register specification in various formats of your choice. Here is what it can do (picture below):

If you thought it can only be for Verification team, be ready for more: it generates:

• RTL code (for Reg RD/WR)
• C-headers for SW team
• UVM/VMM/OVM code for Verif teams
• Assertions
• Functional coverage etc.

All this and more for almost free – Yes indeed! They now offer a free version of their popular IDS for even “commercial use” – see: http://www.agnisys.com/products/66-idsfree 

Aldec’s Riviera-Pro brings UVM, OVM & VMM to desktop & on Cloud!

If you thought all the buzz around SystemVerilog, VMM/OVM/UVM is all for ASIC folks on Linux alone, be ready for some pleasant surprise! Aldec with its much praised easy-to-use tools like Active-HDL, ALINT etc. has built Riviera-Pro to bring these technologies to your laptops/desktops under Windows (and Linux of-course). Their intuitive debug and code-entry features are now available for SystemVerilog/UVM too. Do visit them at their booth or register via:http://www.aldec.com/en/events/sessions/38 to learn more about their debug features such as Transaction Recording, message displays etc.

Also they recently introduced Aldec Cloud – perhaps a bold step towards UVM on cloud!

 

Checkout their free trial @ http://www.aldec.com/en/solutions/functional_verification/aldec_cloud

Axiom’s MPSim & DesignerUVM – the latest in UVM tools!

If you were following the availability of multi-threaded simulators in the market, it is quite possible that you had noticed the front runner in this space – the MPSim from Axiom.  MPSim was the very first one to address the multi-core simulations in EDA domain and since then have grown leaps and bounds to become a strong SystemVerilog simulator with all methodologies such as VMM/OVM and UVM. It also has low power features like UPF that makes it a very compelling product for ASIC houses with large simulation requirements. Axiom is known for performance, but not just that!. It is infact their added debug capability that makes them even more compelling alternative to other vendors. In this Video interview, Tarak from Axiom explains their new debug feature DesignerUVM. 

Quoting Tarak: “You can do lot of simulations, but ultimately the engineering productivity comes from the ability to debug designs”:

We couldn’t agree more! It is Debug that takes whole lot of time and it is quite unfortunate major EDA vendors have not focused their R&D energy on this as much as they perhaps should. Consider the following scenarios in UVM environments:

• A factory override didn’t occur/work as you expected it to
• get_config_string failed to fecth correct value
• In an array of virtual interfaces being hooked up to physical interfaces, something went wrong and you observe incorrect drives/samples
• Port-to-export connections seem wrong

Does your existing Debugger(s) assist you in finding this? (besides gvim/Emacs, find, grep etc.)? If not – it is time to wake up and yell for more from your vendor. Now they have a reason to listen to you – as otherwise YOU as a customer have an alternate – the Axiom DesignerUVM will do these for you!

Breker Systems – SoC level verification

Breker with its new TrekSoC is one of the hottest EDA solutions to watch for – given the huge increase in number of System-On-Chips (SoC) being designed/integrated. Ask yourself:

• How long can you continue with manually written C-tests?
• How long can you maintain 2 (or more) test-env
  • One for Transaction/UVM based and
  • Another for the actual processor RTL based, that require C-tests?
• What about multi-threaded tests? Can we even write them by hand and synchronize?
• Won’t it be nice to have a “single source” for both TXN tests & C-tests?
• Can we truly “reuse” knowledge from IP DITL (Day In The Life) to SoC?
• Can we quickly reproduce SoC level issues at IP level with know extra effort?

These are just some of the “tip-of-the-iceberg” problems of SoC level verification that Breker is attempting to solve for you! For sure you don’t want to miss this – if you are in SoC world (who isn’t BTW?)

Cadence’s AVIP – Accelerated VIP, next form of “Synthesizable VIP”?

For quite a while the industry has been talking about “Synthesizable VIPs” for the want of putting them into FPGAs/Emulators and get more cycles out of DV tasks. VMM started it with VMM-HAL, then came the flurry of Virtual prototypes/platforms that promise to allow smooth integration of various abstraction models in a simulation/emulation env. Cadence’s recent announcement on AVIP is worth noting in this space, see them at DAC for more.

Mentor’s UVM Express, UVMConnect & more..

Mentor recently announced their extended UVM initiatives via UVM Express & UVM Connect:

Their Verification Academy initiative continues to be very popular among users, even non-Mentor customers. Hats off to Dave Rich for keeping the quality of discussions/responses very neutral and technical!

 

NextOp – Assertion Synthesis/Mesh generation

Whether you are doing IP level verification, sub-system or SoC – assertions are your friends – to detect bugs close to the source, apply formal search, indicate coverage holes etc. One of the biggest challenges in adopting them however is – who will write them? This ONE BIG Question has kept the ABV adoption way too slow for too long a period in the industry. But no longer..hopefully if your company can invest in right technology. NextOp with its patented “Assertion Synthesis” can provide you high quality properties:

Yunshan, CEO of NextOp will be in John’s Troublemaker panel, so be there to hear him or ask him live at DAC.

SparkEDA – Ignite your Verification

A quiet storm in the making, SparKEDA spearheaded by Alex Gnusin is creating some very interesting solutions. Its Panda Formal verifier claims simplicity all along. What we really liked on their demo to TeamCVC was their “ASTRA Wave” – an assertion & document creator straight from waveforms, see below for a screenshot. If it works as handy as it promises/claims – this is worth an addition to every Desktop indeed!

 

Specman is alive & kicking in 2012!

In quite contrast to the very many who believed that Specman & the e-language is dead – it is alive and kicking even well into 2012! See various views at DeepChip pages if you wish. But the ground reality from India and Europe is that there are millions of lines of e-code and more is being written as we speak – some by our own TeamCVC for local customers here who simply refuse to move away from the all powerful IEEE 1647 e-language. The eWG http://standards.ieee.org/develop/wg/eWG.html has recently finished its latest LRM updates (read: http://www.cvcblr.com/blog/?p=333). Cadence continues its updates to Specman with features like:

• Parallel compile
• Compiled mode debug
• Save-restore, reseed on the fly etc.

The latest ClubT was held in Israel in Mar 2012 and hopefully sometime soon in India as well!

Synopsys DAC updates

Since the recent nSys acquisition, Synopsys’s VIP portfolio has become very strong and one can expect more native UVM VIPs from them soon. For DAC 2012 specifically their AMS story sounds interesting: http://bit.ly/KYVIBj

On “Verification Luncheon” they plan to talk about SoC level verification. Sure they would showcase the performance improvements to VCS, but hopefully they will also demo their approach to the manual C-test creation monster soon!

UVM 1.1b is almost there

Most of you are following the UVM development at Accellera and DAC is a great time to release a high quality version of ever growing UVM code base. Learn more about what’s new, and what’s lined up for UVM 1.2 etc. at: http://www.accellera.org/downloads/standards/uvm

What about UVM-like for VHDL users?

If you are a VHDL user and have been feeling let down by the marketing bigwigs of EDA vendors – don’t worry, here is OS-VVM for you: Originating from VHDL guru Jim Lewis through his several years of experience, OS-VMM provides:

• Constrained Random generation
• Coverage Model capturing

all in native VHDL. Add this to the most powerful temporal languages available for hardware design industry – the IEEE 1850 PSL – it is a great compelling solution for VHDL users indeed. BTW – if you didn’t know, VHDL 2008 version already incorporates PSL into it, so you just a VHDL license with your EDA tool to run ABV, CRV & CDV (unlike the relatively expensive SystemVerilog solutions), learn more at: http://www.cvcblr.com/blog/?p=436 

Other interesting ones:

Here are some of the other ones you might be interested in:

• EVE – its ZeBu is making more news
• Blue Pearl  -relatively new entrant made some noise about generating SDC/Constraints etc.
• Xilinx’s new Vivado is in the news for its latest SystemVerilog additions and all new ISIM simulator. It is yet to be seen how much UVM support they will add in ISM in years to come.
• RealIntent’s X-finder is another niche point tool that some of you may like!
• UVM Linter from AMIQ

 

Technorati Tags: EDA,Specman,SystemVerilog,DAC

A fairy tale on SystemVerilog MDAs and UVM field macros

 

In one of the semiconductor conferences, Dr. Satya Gupta http://bit.ly/KlQpxr mentioned on a lighter note that the Semiconductor/VLSI needs to be promoted more among young Indian engineers and need to be made more “attractive”. (Guess it was Mentor’s U-2-U in 2010, anyone?) – few of the panelists and audience threw out ideas on how to do the same – via contests, TV shows etc. Taking it little more seriously and using social media we at CVC (www.cvcblr.com) believe our blogs/tweets & Facebook updates are doing exactly that.

Here is a “fairy tale” on how SystemVerilog MDAs work (or not work) with UVM field macros. Consider that we have a 3-D array (2 unpacked dimensions and 1 packed dimension) as shown below (“mda_3d” in s2p_xactn below):

While it sounds simple enough, the devil lies in “detail”. When you need to copy/clone/compare you need to ensure this mda_3d is included just like other fields. Huh? That’s what UVM supports via “field_macros” isn’t it? How about:

 

Oh my dear! Hold your breadth – this works for scalar types, and for 1-D arrays but NOT beyond :-( . Since System Verilog supports “arbitrary” dimensions in MDAs (Multi-Dimensional Arrays), the UVM base class doesn’t provide macros beyond 1-D arrays. Bummer, so what’s next? Here is your helpline – the uvm_object::do_copy.

Here is a simple code snippet that augments the built-in automated “copy” routine to include user defined MDA such as our “mda_3d”.

 

 

With that – UVM has once again proven that while it is not obvious why it has so many hidden “gems” – they are all useful on a case-to-case basis. In Hindi we say “Har eak cheez zaroori hota hai”. As the popular AirTel advertisement goes (India specific, for International readers, see: AirTel commercial ad). In case you can related your facebook friends to UVM “features/functions/base classes” and wonder “How come I have so many friends” – as the ad says “Every friend is useful”

 

 

Happy UVM-ing.

TeamCVC

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