Mind the GAP – even in SystemVerilog macro definition

SystemVerilog enhances the TEXT-MACRO feature (a.k.a `define-s by many young engineers) of Verilog by a good length. Significant enhancements done are:

1. Added capability to extend the definition to multiple lines
2. Added macros with arguments;
3. Macro arguments can have default values too! (not fully supported by all tools though)

However there are few caveats – in general any text-macro usage in any computer language is hard to debug when it fails to compile. So be ready to be patient while debugging macro code.

Recently an online forum user asked a question on SystemVerilog macros. Here is what the user defined to start with:

To a bare eye, the above looks fine. However a  SV compiler would through an error at it. As per the LRM:

 

If formal arguments are used, the list of formal argument names shall be enclosed in parentheses following
the name of the macro. The left parenthesis shall follow the text macro name immediately, with no space in
between.

In other words – as it is with any Metro station sign, you should be careful with the GAP/spaces :-)

Notice that “extra space” after the macro name CHECK1 is now gone! This works in Questa 10.2.

So next time when you code your macros – mind the GAP :-)

TeamCVC

Technorati Tags: SystemVerilog,Verilog,EDA

Smart constraint modeling in SystemVerilog

With SystemVerilog language gaining popularity among user, it is getting interesting to see user asking similar/repeating “patterns” of challenges in various forums. One of them is on constraint modeling when it becomes more than simple “a > 10” like stuff. Recently a VerifAcademy user asked:

 

in my testbench i have to make a random signal "[31:0] distortion". it must contain one (or, in other case, two) hot bit(s) (hot bit is "1", all others are "0"). So i have a problem with writing a constraint: i really don't want to write all possible combinations of these bits (if there are two of them, there will be 32! combinations, so...). Does anyone have solution for this problem?

 

A smart model is indeed available via 2 features of this vast language – System Verilog:

1. A handy system function to count the number of “ones”

2. Constraints can use functions in expressions.

Combining the above two, here is a full solution to the above problem along with a sample run from Questa 10.2

 

Hope you enjoy the concise solution. Do call us via +91-9620209226 or training@cvcblr.com for learning more about this wonderful language and its applicability for your verification projects.

TeamCVC

 

 

Technorati Tags: systemVerilog,EDA

SystemVerilog 2009 macro `__FILE__ – absolute or relative path?

As many of our customer learn during our regular VSV training sessions, System Verilog added `__FILE__ & `__LINE__ macros similar to C language. It is quite handy for debugging remotely developed code for a newcomer especially. Recently at an UVM forum a user asked how to get the relative path vs. absolute path from this macro. Consider the following code:

 

The SV LRM says;

22.13 `__FILE__ and `__LINE__
`__FILE__ expands to the name of the current input file, in the form of a string literal. This is the path by
which a tool opened the file,

So if you provide the absolute path name during compile command, you are bound to get the FULL PATH.

Questa when run with full path to the file as below:

produces the following output:

 

And you could get a pretty short output as below if you do a “magic” (Left as exercise to the interested reader :-) )

Enjoy System Verilog and have fun!

TeamCVC 

Technorati Tags: SystemVerilog,EDA