SystemVerilog 2009 macro `__FILE__ – absolute or relative path?

As many of our customer learn during our regular VSV training sessions, System Verilog added `__FILE__ & `__LINE__ macros similar to C language. It is quite handy for debugging remotely developed code for a newcomer especially. Recently at an UVM forum a user asked how to get the relative path vs. absolute path from this macro. Consider the following code:

 

The SV LRM says;

22.13 `__FILE__ and `__LINE__
`__FILE__ expands to the name of the current input file, in the form of a string literal. This is the path by
which a tool opened the file,

So if you provide the absolute path name during compile command, you are bound to get the FULL PATH.

Questa when run with full path to the file as below:

produces the following output:

 

And you could get a pretty short output as below if you do a “magic” (Left as exercise to the interested reader :-) )

Enjoy System Verilog and have fun!

TeamCVC 

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