Fast-Track course on Verification Using SystemVerilog - Hyderabad

Fast-Track course on Verification Using SystemVerilog - Hyderabad

Quick facts
When: 12th (or) 13th July (Sat/Sun)

Cost: Rs. 4000 /-

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s SystemVerilog?
IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.

What’s a Fast-Track course?
A Fast-Track process is intended to cut short detailed explanations aimed at getting to the core of the subject ASAP. CVC’s Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.

Who should attend?
Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV in 1-day without bothering about the nitty-gritty in great detail.

What’s the cost?
The basic cost of this course is Rs. 4,000 /- + ST (12.36 %) per attendee.

Terms & Conditions
· In general we require that the fee is paid in 100% prior to the start of the training.
· For large corporate with more number of attendees to account for their internal process we do allow an exception to the above rule; however we charge an additional 25% of the training cost per attendee in such cases. In case the fee is paid after the training, the payment should be made within 1 week after the training is delivered. Any additional delay shall be charged at 10% every additional day.
· Any "offer" price mentioned in the course announcement is applicable only for individual attendees and not for corporate.

Cancellation Policy
Course tuition is fully refundable up to one week before the class starts. Cancellations within a week (2-7 days) of the class start date will incur a 50% cancellation fee. Those who cancel fewer than 2 days prior to the class will be billed for the full amount of the tuition. A no-show will be treated as cancellation and no refund shall be given. For genuine cases of absence, we can provide a training token that the trainee can avail in one of the future training classes subject to space availability.

How do I register for a class?
To attend this class, confirm your registration by sending an email to cvc.training @ gmail.com. +91-9916176014, +91-80-41495572
Please include the following details in your email:
Name:

Company Name:

Official Email ID:

Contact Number:
Preferred Date: 12th (or) 13th July (Saturday or Sunday)

Are there extended versions of these courses?
Of-course yes! Our flagship trainings on Verification Using SystemVerilog are originally designed for 3 variants:
· 10-day class with extensive labs and a complete project (suitable for students, jobseekers)
· 3-day class and
· 2-day class
So, depending on how much time you can invest, you pick the one appropriate to you. Needless to say – the more time you invest, the better you master this amazingly powerful language.

Trainer Profile

Ajeetha Kumari, Design Verification Consultant
· Has 8+ years of experience in Verification
· Co-authored leading books in the Verification domain.
· Presented papers, tutorials in various conferences, publications andavenues.
· Worked with all leading edge simulators and formal verification(Model Checking) tools.
· Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDVand OOP for Verification
· Holds M.S.E.E. from prestigious IIT, Madras.

Fast-Track course on Verification Using SystemVerilog - Hyderabad

Fast-Track course on Verification Using SystemVerilog - Hyderabad

Quick facts
When: 13th /14th July (Sun/Mon)
Where: Hyderabad

Cost: Rs. 4000 /-

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s SystemVerilog?
IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.

What’s a Fast-Track course?
A Fast-Track process is intended to cut short detailed explanations aimed at getting to the core of the subject ASAP. CVC’s Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.

Who should attend?
Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV in 1-day without bothering about the nitty-gritty in great detail.

What’s the cost?
The basic cost of this course is Rs. 4,000 /- + ST (12.36 %) per attendee.

Terms & Conditions
· In general we require that the fee is paid in 100% prior to the start of the training.
· For large corporate with more number of attendees to account for their internal process we do allow an exception to the above rule; however we charge an additional 25% of the training cost per attendee in such cases. In case the fee is paid after the training, the payment should be made within 1 week after the training is delivered. Any additional delay shall be charged at 10% every additional day.
· Any "offer" price mentioned in the course announcement is applicable only for individual attendees and not for corporate.

Cancellation Policy
Course tuition is fully refundable up to one week before the class starts. Cancellations within a week (2-7 days) of the class start date will incur a 50% cancellation fee. Those who cancel fewer than 2 days prior to the class will be billed for the full amount of the tuition. A no-show will be treated as cancellation and no refund shall be given. For genuine cases of absence, we can provide a training token that the trainee can avail in one of the future training classes subject to space availability.

How do I register for a class?
To attend this class, confirm your registration by sending an email to cvc.training@gmail.com. +91-9916176014, +91-80-41495572
Please include the following details in your email:
Name:

Company Name:

Official Email ID:

Contact Number:
Preferred Date: 13th or 14th July (Sunday or Monday)

Are there extended versions of these courses?
Of-course yes! Our flagship trainings on Verification Using SystemVerilog are originally designed for 3 variants:
· 10-day class with extensive labs and a complete project (suitable for students, jobseekers)
· 3-day class and
· 2-day class
So, depending on how much time you can invest, you pick the one appropriate to you. Needless to say – the more time you invest, the better you master this amazingly powerful language.

Trainer Profile

Ajeetha Kumari, Design Verification Consultant
· Has 8+ years of experience in Verification
· Co-authored leading books in the Verification domain.
· Presented papers, tutorials in various conferences, publications andavenues.
· Worked with all leading edge simulators and formal verification(Model Checking) tools.
· Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDVand OOP for Verification
· Holds M.S.E.E. from prestigious IIT, Madras.


Other Trainings:

• Comprehensive Functional Verification (CFV)

This course is a jump start, meant for entry level which is unique of its kind and it covers the aspects of Verification in one day. It provides you the best platform to start a career in Functional Verification. By attending this course you will understand the nuances of FV.

Languages

• IEEE 1800 SystemVerilog Design (SVD)
  
• IEEE 1800 SystemVerilog Assertions (SVA)
• IEEE 1800 SystemVerilog for Verification (SVTB)
• IEEE 1850 Property Specification Language (PSL)
• IEEE 1647, e-language
• IEEE 1364 Verilog
• IEEE 1076 VHDL
  

Methodology

• IEEE 1800 - SV Based Verification Methodology Manual (VMM)
• IEEE 1800 - SV Based Open Verification Methodology (OVM)
  
• Assertion Based Verification (ABV)
• Coverage Driven Verification (CDV)
  

Workshops

• Gate Level Simulation
• ABV beyond RTL
• OOP Basics
  

Fast-Track course on Verification Using SystemVerilog - Bangalore

Fast-Track course on Verification Using SystemVerilog - Bangalore

Quick facts
When: 19th /20th June (Thurs/Fri)
Where: Bangalore, CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)

Cost: Rs. 4000 /-

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s SystemVerilog?
IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.

What’s a Fast-Track course?
A Fast-Track process is intended to cut short detailed explanations aimed at getting to the core of the subject ASAP. CVC’s Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.

Who should attend?
Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV in 1-day without bothering about the nitty-gritty in great detail.

What’s the cost?
The basic cost of this course is Rs. 4,000 /- + ST (12.36 %) per attendee.

Terms & Conditions
· In general we require that the fee is paid in 100% prior to the start of the training.
· For large corporate with more number of attendees to account for their internal process we do allow an exception to the above rule; however we charge an additional 25% of the training cost per attendee in such cases. In case the fee is paid after the training, the payment should be made within 1 week after the training is delivered. Any additional delay shall be charged at 10% every additional day.
· Any "offer" price mentioned in the course announcement is applicable only for individual attendees and not for corporate.

Cancellation Policy
Course tuition is fully refundable up to one week before the class starts. Cancellations within a week (2-7 days) of the class start date will incur a 50% cancellation fee. Those who cancel fewer than 2 days prior to the class will be billed for the full amount of the tuition. A no-show will be treated as cancellation and no refund shall be given. For genuine cases of absence, we can provide a training token that the trainee can avail in one of the future training classes subject to space availability.

Venue details
CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Date: 2 potential dates:
Friday 20th June at 8.30 AM
Saturday 21st June at 8.30 AM

How do I register for a class?
To attend this class, confirm your registration by sending an email to cvc.training @ gmail.com. +91-9916176014, +91-80-41495572
Please include the following details in your email:
Name:

Company Name:

Official Email ID:

Contact Number:
Preferred Date: 20th or 21st June (Friday or Saturday)

Are there extended versions of these courses?
Of-course yes! Our flagship trainings on Verification Using SystemVerilog are originally designed for 3 variants:
· 10-day class with extensive labs and a complete project (suitable for students, jobseekers)
· 3-day class and
· 2-day class
So, depending on how much time you can invest, you pick the one appropriate to you. Needless to say – the more time you invest, the better you master this amazingly powerful language.

Trainer Profile

Ajeetha Kumari, Design Verification Consultant
· Has 8+ years of experience in Verification
· Co-authored leading books in the Verification domain.
· Presented papers, tutorials in various conferences, publications andavenues.
· Worked with all leading edge simulators and formal verification(Model Checking) tools.
· Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDVand OOP for Verification
· Holds M.S.E.E. from prestigious IIT, Madras.

Fast-Track course on Verification Using SystemVerilog - Bangalore

Fast-Track course on Verification Using SystemVerilog - Bangalore

Quick facts

When: 6^th or 7^th June (Fri/Sat)

Where: Bangalore, CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Cost: Rs. 2500 /- onwards (See below for details)

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s SystemVerilog?

IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.

What’s a Fast-Track course?

A Fast-Track process is intended to cut short detailed explanations aimed at getting to the core of the subject ASAP. CVC’s Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.

Who should attend?

Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV in 1-day without bothering about the nitty-gritty in great detail.

What’s the cost?

That is a no-brainer question, isn’t it? We understand and appreciate the cost conscious landscape of our region. That’s why we have innovative cost structure as shown below.

The basic cost of this course is Rs. 4,000 /- per attendee. As a limited period offer, we are glad to announce “The more-the-merrier” scheme. If you pool in more folks you get more discounts. For every other attendee that you bring along, you get Rs. 500 /- discount – for BOTH the attendees (subjected to a minimum of Rs. 2500 /-), can it get better than this :-) ?

Here is a simple table showing the offer in numeric:

No. of attendees | Cost per attendee | Your savings (total)

2 3500 1000

3 3000 3000

4 (and above) 2500 6000+

Venue details

CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Date: 2 potential dates:

Friday 6^th June at 8.30 AM

Saturday 7^th June at 8.30 AM

How do I register for a class?

To attend this class, confirm your registration by sending an email to cvc.training @ gmail.com. +91-9916176014, +91-80-41495572

Please include the following details in your email:

Name:
Company Name:
Official Email ID:
Contact Number:

Preferred Date: 6^th or 7^th June (Friday or Saturday)

Are there extended versions of these courses?

Of-course yes! Our flagship trainings on Verification Using SystemVerilog are originally designed for 3 variants:

• · A 10-day class with extensive labs and a complete project (suitable for students, jobseekers)
• · A 3-day class and
• · A 2-day class

So, depending on how much time you can invest, you pick the one appropriate to you. Needless to say – the more time you invest, the better you master this amazingly powerful language.

Trainer Profile
Ajeetha Kumari, Design Verification Consultant
* Has 8+ years of experience in Verification
* Co-authored leading books in the Verification domain.
* Presented papers, tutorials in various conferences, publications and
avenues.
* Worked with all leading edge simulators and formal verification
(Model Checking) tools.
* Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV
and OOP for Verification
* Holds M.S.E.E. from prestigious IIT, Madras.