Friday, October 24, 2008

SV care-abouts with disable iff construct

During our SystemVerilog Assertions handbook writing, we identified a set of guidelines for effective coding of complex, scalabe properties.



Some of them have to deal with handling abort conditions during a property evaluation. In any practical protocol used to transfer data across, typical transfers occur over several clock cycles. There are situations where-in an abort condition triggers and ongoing evaluations needs to be aborted/terminated. IEEE 1800 SystemVerilog provides disable iff construct to model this. A sample code:




Now consider the case that the aborting condition is not a simple signal, rather a temporal sequence. One might think of adding a sequence inside disable iff but that's illegal as per LRM. You typically get errors like:

// Tool errors out
// See: http://www.verificationguild.com/modules.php?name=Forums&file=viewtopic&t=2889

Sequence or property instance used in a non-temporal context
//

So how do you model an abort sequence then? Consider a temporal behavior being verified as shown below:



Now consider an abort sequence as in:




So how do you model this? SystemVerilog allows sequence.triggered inside disable iff. So you can do:

a_p_mstr_xfer : assert property (disable iff (mstr_abort_seq.triggered) p_mstr_xfer);

Enjoy SystemVerilog!

Ajeetha, CVC
www.noveldv.com

Tuesday, July 22, 2008

Free Seminar on "Quest for Scalable Verification => result:Questa + OVM "


Free Seminar on "Quest for Scalable Verification => result:Questa + OVM "

With ever growing complexities of ASICs (and FPGAs), the task of verifying them has become a “never-say-done” activity. Given the need for multiple levels of reuse in design and verification, a stand-still approach to verification doesn’t hold good any longer. It requires continuous inflow of new ideas, thoughts and technologies to address the complex requirements. Hence the quest for a scalable verification has been a continuous one. A series of innovative, path breaking technologies have emerged over the last decade to address the verification challenges. Back in 2005 IEEE standardized SystemVerilog as the standard HDVL to incorporate many of these technologies with a Verilog flavor. Since then SV has been making its way into being the most preferred language for ASIC Design and Verification across the globe. However leading edge semiconductor houses have quickly realized that using SystemVerilog on its own might lead to sub-optimal benefits especially in Verification. This is due to the fact that the language is vast and not every team has enough time to experiment with the right usage model for the task at hand. This is the primary motivation behind adopting a Verification Methodology - to get more productive in less time.

OVM as announced in late 2007/early 2008 is proving to be a very good choice for building such scalable verification infrastructure as it has all the classical methodology features plus some of the most advanced, proven verification techniques such as Virtual sequences, factories etc. The good thing about OVM is it is open, and there is a vibrant ecosystem building around OVM. We at CVC have an everlasting thirst to be on top of any new verification technology. As part of Mentor’s Questa Vanguard program, CVC has had the privilege of experiencing the power of OVM early with a robust, easy-to-use verification platform – Questa!

As with any new technology, the initial adoption requires some ramp up time. During our early engagements with building OVM compliant verification environments we went through a series of learning steps. As a result of it, we at CVC recently composed a step-by-step OVM quick start guide that we share with our customers. In this seminar, we share an early preview of this step-by-step guide with a simple packet de-serializer design. We walk through the following topics:

  • SystemVerilog features for Verification
  • OVM introduction
  • DUV - Packet de-serializer
  • Step-by-step OVM approach with code snippets
  • Highlights of important Questa features that helped us in the process
  • Results, summary and looking forward

To attend this seminar: Click on: Register for CVC OVM with Questa seminar. If the above link doesn’t work, send an email to mailto:cvc.training@gmail.com;?subject=CVC_OVM_Questa Please include the following details in your email.

Name:
Company Name:
Official Email ID:
Contact Number:

Venue: CVC Bangalore Office (Ground Floor)

Date: 2nd Aug 2008, Saturday at 15.00 (3.00 PM)

Agenda: 1 hour presentation followed by a quick demo + Q&A

Friday, July 18, 2008

Bangalore, July 23rd: Free seminar on: Advanced Verification with Aldec’s Riviera-PRO - with SystemVerilog

Advanced Verification with Aldec’s Riviera-PRO

Given the ever growing complexities of SoC designs, the task of verifying these SoCs is herculean indeed! A series of innovative, path breaking technologies have emerged over the last decade to address the verification challenges. Industry is seeing a culmination of these techniques in the form of new languages such as IEEE 1850-PSL, IEEE 1666 SystemC etc. Every language provides a complementary strength, and addresses specific problem. Recently, many of these separate language capabilities have been integrated into single language and are available as IEEE-1800 standard SystemVerilog (SV). SV is poised to be the choice of DV engineers for many years to come due to the overwhelming support from all tools and the greater eco-system of trainings, books and papers.

Aldec has been the primary EDA provider for various ASIC and FPGA design tasks for 24 years by now. Riviera-PRO is a proven high-performance, mixed-language simulation engine with advanced debugging tools for ASIC and FPGA design teams. Riviera-PRO supports VHDL, Verilog®, SystemVerilog, SystemC, C/C++, PSL and OVA assertions from one common design environment. Riviera-PRO enables mixed RTL debugging, long regression testing, timing simulation and electronic system level (ESL) verification.

IEEE 1800, SystemVerilog is a major extension to Verilog-2001, adding significant new features to Verilog for verification, design and synthesis. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of a
complete Object-Oriented paradigm features. We at CVC have been on the top of leading edge verification technologies for the past half-a-decade. We recently setup an advanced verification environment for a memory controller using SystemVerilog and Aldec’s Riviera-PRO. In this seminar and share that anecdote with the attendees. We walk through the following topics:

· Advanced Verification techniques

· Verification Architecture for Memory controller

· Key SystemVerilog features used in this verification with code snippets

· Screenshots of important Riviera-PRO features that helped us in the process

To attend this seminar, confirm your registration by sending an email to cvc.training@noveldv.com , cvc.training@gmail.com with subject as CVC_Verif_Aldec Seminar. Please include the following details in your email.

Name:
Company Name:
Official Email ID:
Contact Number:

Venue: CVC Office (Ground Floor)

Date: 23rd July 2008 at 11.00 A.M
Agenda: 1 hour presentation on Advanced Verification Using Aldec followed by demo

Monday, June 30, 2008

Fast-Track course on Verification Using SystemVerilog - Hyderabad

Fast-Track course on Verification Using SystemVerilog - Hyderabad


Quick facts
When: 12th (or) 13th July (Sat/Sun)

Cost: Rs. 4000 /-

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s SystemVerilog?
IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.

What’s a Fast-Track course?
A Fast-Track process is intended to cut short detailed explanations aimed at getting to the core of the subject ASAP. CVC’s Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.

Who should attend?
Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV in 1-day without bothering about the nitty-gritty in great detail.

What’s the cost?
The basic cost of this course is Rs. 4,000 /- + ST (12.36 %) per attendee.

Terms & Conditions
· In general we require that the fee is paid in 100% prior to the start of the training.
· For large corporate with more number of attendees to account for their internal process we do allow an exception to the above rule; however we charge an additional 25% of the training cost per attendee in such cases. In case the fee is paid after the training, the payment should be made within 1 week after the training is delivered. Any additional delay shall be charged at 10% every additional day.
· Any "offer" price mentioned in the course announcement is applicable only for individual attendees and not for corporate.


Cancellation Policy
Course tuition is fully refundable up to one week before the class starts. Cancellations within a week (2-7 days) of the class start date will incur a 50% cancellation fee. Those who cancel fewer than 2 days prior to the class will be billed for the full amount of the tuition. A no-show will be treated as cancellation and no refund shall be given. For genuine cases of absence, we can provide a training token that the trainee can avail in one of the future training classes subject to space availability.

How do I register for a class?
To attend this class, confirm your registration by sending an email to cvc.training @ gmail.com. +91-9916176014, +91-80-41495572
Please include the following details in your email:
Name:

Company Name:

Official Email ID:

Contact Number:
Preferred Date: 12th (or) 13th July (Saturday or Sunday)

Are there extended versions of these courses?
Of-course yes! Our flagship trainings on Verification Using SystemVerilog are originally designed for 3 variants:
· 10-day class with extensive labs and a complete project (suitable for students, jobseekers)
· 3-day class and
· 2-day class
So, depending on how much time you can invest, you pick the one appropriate to you. Needless to say – the more time you invest, the better you master this amazingly powerful language.

Trainer Profile

Ajeetha Kumari, Design Verification Consultant
· Has 8+ years of experience in Verification
· Co-authored leading books in the Verification domain.
· Presented papers, tutorials in various conferences, publications andavenues.
· Worked with all leading edge simulators and formal verification(Model Checking) tools.
· Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDVand OOP for Verification
· Holds M.S.E.E. from prestigious IIT, Madras.

Monday, June 23, 2008

Fast-Track course on Verification Using SystemVerilog - Hyderabad


Fast-Track course on Verification Using SystemVerilog - Hyderabad


Quick facts
When: 13th /14th July (Sun/Mon)
Where: Hyderabad

Cost: Rs. 4000 /-

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s SystemVerilog?
IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.

What’s a Fast-Track course?
A Fast-Track process is intended to cut short detailed explanations aimed at getting to the core of the subject ASAP. CVC’s Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.

Who should attend?
Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV in 1-day without bothering about the nitty-gritty in great detail.

What’s the cost?
The basic cost of this course is Rs. 4,000 /- + ST (12.36 %) per attendee.

Terms & Conditions
· In general we require that the fee is paid in 100% prior to the start of the training.
· For large corporate with more number of attendees to account for their internal process we do allow an exception to the above rule; however we charge an additional 25% of the training cost per attendee in such cases. In case the fee is paid after the training, the payment should be made within 1 week after the training is delivered. Any additional delay shall be charged at 10% every additional day.
· Any "offer" price mentioned in the course announcement is applicable only for individual attendees and not for corporate.


Cancellation Policy
Course tuition is fully refundable up to one week before the class starts. Cancellations within a week (2-7 days) of the class start date will incur a 50% cancellation fee. Those who cancel fewer than 2 days prior to the class will be billed for the full amount of the tuition. A no-show will be treated as cancellation and no refund shall be given. For genuine cases of absence, we can provide a training token that the trainee can avail in one of the future training classes subject to space availability.

How do I register for a class?
To attend this class, confirm your registration by sending an email to cvc.training@gmail.com. +91-9916176014, +91-80-41495572
Please include the following details in your email:
Name:

Company Name:

Official Email ID:

Contact Number:
Preferred Date: 13th or 14th July (Sunday or Monday)

Are there extended versions of these courses?
Of-course yes! Our flagship trainings on Verification Using SystemVerilog are originally designed for 3 variants:
· 10-day class with extensive labs and a complete project (suitable for students, jobseekers)
· 3-day class and
· 2-day class
So, depending on how much time you can invest, you pick the one appropriate to you. Needless to say – the more time you invest, the better you master this amazingly powerful language.

Trainer Profile

Ajeetha Kumari, Design Verification Consultant
· Has 8+ years of experience in Verification
· Co-authored leading books in the Verification domain.
· Presented papers, tutorials in various conferences, publications andavenues.
· Worked with all leading edge simulators and formal verification(Model Checking) tools.
· Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDVand OOP for Verification
· Holds M.S.E.E. from prestigious IIT, Madras.


Other Trainings:
  • Comprehensive Functional Verification (CFV)
This course is a jump start, meant for entry level which is unique of its kind and it covers the aspects of Verification in one day. It provides you the best platform to start a career in Functional Verification. By attending this course you will understand the nuances of FV.

Languages

  • IEEE 1800 SystemVerilog Design (SVD)
  • IEEE 1800 SystemVerilog Assertions (SVA)
  • IEEE 1800 SystemVerilog for Verification (SVTB)
  • IEEE 1850 Property Specification Language (PSL)
  • IEEE 1647, e-language
  • IEEE 1364 Verilog
  • IEEE 1076 VHDL
Methodology
  • IEEE 1800 - SV Based Verification Methodology Manual (VMM)
  • IEEE 1800 - SV Based Open Verification Methodology (OVM)
  • Assertion Based Verification (ABV)
  • Coverage Driven Verification (CDV)
Workshops
  • Gate Level Simulation
  • ABV beyond RTL
  • OOP Basics


Sunday, June 15, 2008

Fast-Track course on Verification Using SystemVerilog - Bangalore

Fast-Track course on Verification Using SystemVerilog - Bangalore


Quick facts
When: 19th /20th June (Thurs/Fri)
Where: Bangalore, CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)

Cost: Rs. 4000 /-

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s SystemVerilog?
IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.

What’s a Fast-Track course?
A Fast-Track process is intended to cut short detailed explanations aimed at getting to the core of the subject ASAP. CVC’s Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.

Who should attend?
Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV in 1-day without bothering about the nitty-gritty in great detail.

What’s the cost?
The basic cost of this course is Rs. 4,000 /- + ST (12.36 %) per attendee.

Terms & Conditions
· In general we require that the fee is paid in 100% prior to the start of the training.
· For large corporate with more number of attendees to account for their internal process we do allow an exception to the above rule; however we charge an additional 25% of the training cost per attendee in such cases. In case the fee is paid after the training, the payment should be made within 1 week after the training is delivered. Any additional delay shall be charged at 10% every additional day.
· Any "offer" price mentioned in the course announcement is applicable only for individual attendees and not for corporate.


Cancellation Policy
Course tuition is fully refundable up to one week before the class starts. Cancellations within a week (2-7 days) of the class start date will incur a 50% cancellation fee. Those who cancel fewer than 2 days prior to the class will be billed for the full amount of the tuition. A no-show will be treated as cancellation and no refund shall be given. For genuine cases of absence, we can provide a training token that the trainee can avail in one of the future training classes subject to space availability.

Venue details
CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Date: 2 potential dates:
Friday 20th June at 8.30 AM
Saturday 21st June at 8.30 AM

How do I register for a class?
To attend this class, confirm your registration by sending an email to cvc.training @ gmail.com. +91-9916176014, +91-80-41495572
Please include the following details in your email:
Name:

Company Name:

Official Email ID:

Contact Number:
Preferred Date: 20th or 21st June (Friday or Saturday)

Are there extended versions of these courses?
Of-course yes! Our flagship trainings on Verification Using SystemVerilog are originally designed for 3 variants:
· 10-day class with extensive labs and a complete project (suitable for students, jobseekers)
· 3-day class and
· 2-day class
So, depending on how much time you can invest, you pick the one appropriate to you. Needless to say – the more time you invest, the better you master this amazingly powerful language.

Trainer Profile

Ajeetha Kumari, Design Verification Consultant
· Has 8+ years of experience in Verification
· Co-authored leading books in the Verification domain.
· Presented papers, tutorials in various conferences, publications andavenues.
· Worked with all leading edge simulators and formal verification(Model Checking) tools.
· Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDVand OOP for Verification
· Holds M.S.E.E. from prestigious IIT, Madras.

Sunday, June 1, 2008

Fast-Track course on Verification Using SystemVerilog - Bangalore

Fast-Track course on Verification Using SystemVerilog - Bangalore

Quick facts

When: 6th or 7th June (Fri/Sat)

Where: Bangalore, CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Cost: Rs. 2500 /- onwards (See below for details)

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-41495572

What’s SystemVerilog?

IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.

What’s a Fast-Track course?

A Fast-Track process is intended to cut short detailed explanations aimed at getting to the core of the subject ASAP. CVC’s Fast-Track courses are intended for engineers with little extra time to spare, yet would like to learn the new and advanced verification techniques. In 1-day we cover the essential sub-set of SystemVerilog and enable to you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification. As it is really time bound we will not delve into rationales on many aspects, instead will focus on getting you hands-on with the language.

Who should attend?

Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV in 1-day without bothering about the nitty-gritty in great detail.

What’s the cost?

That is a no-brainer question, isn’t it? We understand and appreciate the cost conscious landscape of our region. That’s why we have innovative cost structure as shown below.

The basic cost of this course is Rs. 4,000 /- per attendee. As a limited period offer, we are glad to announce “The more-the-merrier” scheme. If you pool in more folks you get more discounts. For every other attendee that you bring along, you get Rs. 500 /- discount – for BOTH the attendees (subjected to a minimum of Rs. 2500 /-), can it get better than this :-) ?

Here is a simple table showing the offer in numeric:

No. of attendees | Cost per attendee | Your savings (total)

2 3500 1000

3 3000 3000

4 (and above) 2500 6000+

Venue details


CVC Office (Ground Floor) (http://www.noveldv.com/contactus.html)
Date: 2 potential dates:

Friday 6th June at 8.30 AM

Saturday 7th June at 8.30 AM

How do I register for a class?

To attend this class, confirm your registration by sending an email to cvc.training @ gmail.com. +91-9916176014, +91-80-41495572

Please include the following details in your email:


Name:
Company Name:
Official Email ID:
Contact Number:

Preferred Date: 6th or 7th June (Friday or Saturday)

Are there extended versions of these courses?


Of-course yes! Our flagship trainings on Verification Using SystemVerilog are originally designed for 3 variants:

  • · A 10-day class with extensive labs and a complete project (suitable for students, jobseekers)
  • · A 3-day class and
  • · A 2-day class

So, depending on how much time you can invest, you pick the one appropriate to you. Needless to say – the more time you invest, the better you master this amazingly powerful language.


Trainer Profile
Ajeetha Kumari, Design Verification Consultant
* Has 8+ years of experience in Verification
* Co-authored leading books in the Verification domain.
* Presented papers, tutorials in various conferences, publications and
avenues.
* Worked with all leading edge simulators and formal verification
(Model Checking) tools.
* Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV
and OOP for Verification
* Holds M.S.E.E. from prestigious IIT, Madras.

Wednesday, May 28, 2008

VMM is for everyone now!

One of the most awaited good news for VLSI Verification community is finally here. VMM is free, open and freely downloadable, Voila!!


http://www.vmmcentral.org/home.html

Enjoy VMMing!

Ajeetha, CVC
www.noveldv.com