Certificate course on SystemVerilog Assertions
…Language + Lab + Mini-project
CVC is announcing a new session of its popular 2-day certificate course on SsystemVerilog Assertions (ABV_SVA) covering SystemVerilog Assertions in depth. Broadly it covers the following topics:
- ABV Introduction
- SystemVerilog Assertions (SVA)
- Project – develop a real life Protocol IP (PIP) with SVA
Course contents: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf
Duration
Here is a detailed breakdown of the course with duration. Note that we have a “mini project” tightly embedded in the course that helps in mastering topics learned so far in the course. This is on top of the regular labs that are part of the training.
| Topic | Duration | Start | End |
| SystemVerilog Assertions | 1.5 days | July 13 | July 14 |
| Mini Project II | 0.5 day | July 14 | July 14 |
Schedule:
July 13, 14 at Bangalore
To attend this class, confirm your registration by sending an email to training @ cvcblr.com
Ph: +91-9916176014, +91-80-42134156
Please include the following details in your email:
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