Here are some snaps from recent DVCon UVM poster session. More than 12 vendors demonstrated their commerical offerings around UVM and it was an electrifying experience for the attendees/potential customers (some 180+ UVM tutorial attendees). Products/offerings broadly fell in the following categories:
- Simulators – Cadence, Synopsys (DOn’t recall Mentor on poster, but of-course Questa supports UVM), another missing poster EDA tool company was Aldec. Though both Mentor & Aldec had their booths at the exhibit.
Cadence had a poster on how IUS supports UVM and extended debug features targeted for UVM users. Here is Joesph H with his Cadence poster
Synopsys had a clear, simple poster on how VCS extends its leadership in SystemVerilog performance. Here is Adiel Khan explaining with passion to a customer Synopsys poster:
- Register model automation, maintenance: AgniSys dominated the poster with lots of visitors asking questions. Infact their poster attracted attendees even after the tutorial break was over and the session re-started. Alas, Anupam wasn’t there, but Srini from CVC (www.cvcblr.com) did some back-up for Anupam. Part of EDA ecosystem, Huh!
Here is Anupam explaining his poster to a customer potential:
Other similar offerings were demonstrated by Semifore & Doulog.
- Trainings: Clearly attendees were well treated by thriving training ecosystem – with CVC (www.cvcblr.com), Doulos and others showing off their new trainings on UVM.
- VIPs: CVC (www.cvcblr.com) launched its latest campaign around UVM aptly named “UnleashingUVM” with trainings, products & services around UVM.
Here is our CTO, Srini (http://www.linkedin.com/in/svenka3) with the poster:
And we had an interesting visitor all the way from home (Bangalore) – Mr. Amit Sharma :-)
Here is a more detailed list of CVC’s products & Services around UVM:
Overall it was a great successful poster session and the user interest around it is a standing testimonial to the overwhelming customer expectation on UVM.
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