If you are curious about recently released UVM standard – you won’t have missed to note the DVCon-2011 blogs/tweets etc. Some of those captures can be seen at http://www.cvcblr.com/blog/?p=283
http://www.cvcblr.com/blog/?p=298
http://www.cvcblr.com/blog/?p=322
Now, in case you didn’t visit DVCon, here is UVM coming to YOU – at Bangalore & Pune. Thanks to Cadence & QLogic, there are free UVM update events being scheduled on Apr 13th & Apr 19th. Register for free right away.
Agenda:
- New UVM 1.0 overview and comparison to OVM
- Important OVM and UVM phasing
- Secrets in mastering OVM and UVM
- Graceful termination of tests in OVM and UVM with emphasis on the objection mechanism
- Some of Cliff's favorite SystemVerilog tips and tricks
- Some early UVM techniques and best practices
Date | Time | Location |
April 13, Wednesday | 2.00pm – 5.30pm | Bangalore Auditorium 1 |
April 19, Tuesday | 4.00 – 7.30pm | Pune, MCCIA Auditorium |
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