Sledgehammer to crack a nut? – Use right tools for right class of design errors/bugs

I am sure you have heard this phrase before – “A sledgehammer to crack a nut”; the below picture describes it all!

Would you use a HUGE hammer to crack a small, tiny nut?

(If you are further interested in this phrase read: http://www.phrases.org.uk/meanings/sledgehammer-to-crack-a-nut.html).

I recently had a small design error introduced in a piece of  RTL as below: It is an interrupt masking logic, code snippet as below:

Note the use of “ANDing” logic – simply, AND- mask with data to produce result.The subtlety in Verilog/System Verilog is that you have 2 seemingly similar operators for doing AND operation;

1. The logical AND: &&
2. The bitwise AND: &

Given the “loose” data type checking, assignment rules etc. one can get away by using either one of the above many-a-times. In the above case the user used:

  result = data && mask;

With result being a vector the above is a “logical/design error” but usually a Verilog compiler would let this go through (as it is not an error as per LRM).

Now one can “verify” this by writing a testbench, simulate, look at waveform and debug. Depending on luck and the expertise of the engineer, it could take some 30-minutes to few hours. But as a Verification power-house CVC suggests to rethink – use the right tool/technology for the right class of design errors. These are things that are very easy for a static verification technology such as HDL-Linting to flag in less than a minute.

For instance, let’s try the above code with a popular Linter – ALINT from Aldec (http://www.aldec.com/products/alint/).

 

ALINT has nice rule sets pre-packaged for various policies such as STARC (http://www.starc.jp/index-e.html). It produces the following:

 

This will trigger 2 rules:
  -  rule about logic operation having a vector operand
  -  rule about bit width mismatch in the assignment - LHS vs RHS.

ALINT: Warning: test.v : (4, 1): Module "top". "STARC_VLOG.2.1.4.5" Logical operator has vector argument(s). Use bit-wise operators for multi-bit arguments and logical operators only for 1-bit arguments. Level: Recommendation 1.
ALINT: Warning: test.v : (4, 1): Module "top". "STARC_VLOG.2.10.3.4" Assignment source bit width "1" is less than destination bit width "8". Upper bits of the right-hand side will be filled with zeroes. Match bit widths exactly to improve the readability of the description. Level: Recommendation 2.

 

Now from a business perspective too – this is a far better option for your management – usually LINT tools are far cost efficient than full blown SystemVerilog simulator(s) such as Aldec’s Riviera-Pro http://www.aldec.com/Riviera

So next time when you receive a RTL code to verify, do yourself a favor by running a quick Lint run before looking for “hard bugs” that demand popular, powerful techniques such as Constrained-random, coverage-driven, UVM based etc.

BTW – CVC offers training sessions (http://www.cvcblr.com/trainings) on Aldec’s ALINT and HDL-Lint in general. Contact us (http://www.cvcblr.com/about_us) to see how we can help your teams!

Happy Verification ahead!

UVM with VMM – first trial of true inter-operability

 

As noted in our recent blog article http://www.cvcblr.com/blog/?p=362 UVM is the first genuine step in the industry towards verification inter-operability. But it has a long way to go before all the VIPs get migrated to UVM – if they do. So there is a strong need to leverage on existing code base such as VMM, OVM & UVM.

Below is a code snippet that shows how we can use both VMM & UVM messaging schemes in same env/code base. As such the code is not magic, is it? But do watch below for the real MAGIC..

 

If not for the inter-op kit, the above code would spit the messages from 2 different schemes and make it very hard for end user to keep track, customize etc.

With UVM & VMM loggers being separate and not “inter-operating” the following user issues may arise:

1. Different formatted messages coming at different lines, making it hard, ugly to read, analyze

2. Complicating data-mining of log files as there are 2 different formats now in same log file

3. Error, Warning counts distributed leading to unreliable FAIL/PASS detection

4. Any customization done by user on formatting needs to be done multiple times

5. Sending to different log files not as easy as it involves 2 different base classes now!

 

Again there are more, let’s get solutions on the table. Here comes the MAGIC: With VCS, try:

The log file now combines the `vmm_note into `uvm_info “magically” and unifies it for the users!

 

 

There is much more to this inter-op kit, see: http://www.vmmcentral.com/uvm_vmm_ik/ 

 

Enjoy UVM and more..

Verification inter-operability beyond UVM

As industry gets ready for adopting UVM with SystemVerilog, there are several practical combinations that come to the fore. One of the important concerns is about the existing code base/VIPs that can be “reused as-is”, yet benefit from various UVM features. For instance consider a VMM based VIP being plugged into a new UVM based env. Several user requirements/expectations arise:

1. Can the UVM & VMM co-exist in same simulation?

2. Can we leverage on single messaging scheme – instead of both `uvm_error & `vmm_error counting on their own, how do we unify them?

3. Can UVM phasing control/synchronize the vmm_xacotr::start/stop_xactor?

4. How does the UVM-Objection work with VMM-Consensus?

5. How do we talk from VMM-channel to UVM components and vice-versa?

6.How does the UVM ACTIVE/PASSIVE mechanism control VMM xactors underneath?

7. Does UVM config mechanism affect the VMM, if yes, how, if not then what do we do?

I am sure there are more. But just enough to get you worried! Thankfully the problem seems to have been acknowledged by the EDA vendors and potential solutions have started emerging. For instance the recently released VMM/UVM inter-op kit from Synopsys is at: http://www.vmmcentral.com/uvm_vmm_ik/

 

Another common requirement from many customers is the ability to mix multiple modeling & verification languages with UVM. Cadence recently donated its version of UVM ML (Multi-Language) to Accellera for potential extension. This contains UVM-SystemC via TLM 2,0 and UVM-e for integrating IEEE 1647-E based eVCs to UVM. Though the industry has publically seen only Cadence’s Specman supporting IEEE 1647-E language, if John’s ESNUG were to be trusted (why not BTW?, see: http://www.deepchip.com/items/0495-02.html), it may be soon that all major vendors release E-support.

As noted in our recent blog, http://www.cvcblr.com/blog/?p=361 the upcoming 2012 year seems to be quite interesting for Verification technologies.