As Indian VLSI industry is hiring at crazy rate for verification, SystemVerilog has emerged as a key differentiator in most of the front-end Verification job roles (see: http://www.linkedin.com/groups?homeNewMember=&gid=3706843). With many engineers adding SV skills to their CVs – the interviewers are getting tougher and smarter in their questions during interviews. Some related to OOP are below, source: http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=4410
As our CEO posted some code snippet to start with -we thought we will assist our junior engineers to ponder around the same and explore more on this topic.
class base_pkt;
bit b1;
virtual function void display;
$display ("base_pkt: b1: %b", this.b1);
endfunction : display
endclass : base_pkt
class extended_pkt extends base_pkt;
bit b2;
virtual function void display;
$display ("extended_pkt: b1: %b b2: %b", this.b1, this.b2);
endfunction : display
virtual function void ext_fn;
$display ("EXT Function");
endfunction : ext_fn
endclass : extended_pkt
class container_c;
base_pkt b_p_0;
function new;
this.b_p_0 = new;
endfunction : new
endclass : container_c
program test;
container_c c_0;
extended_pkt e_p_0;
initial begin : b1
c_0 = new;
e_p_0 = new;
c_0.b_p_0.display;
c_0.b_p_0 = e_p_0;
c_0.b_p_0.display;
$finish;
end : b1
endprogram : test
Some of the advanced questions from http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=4410
- can main access the methods and properties in the base_packet
- can main access the new methods and properties in the extended_packet class as it is or any casting would be needed
- assume one of the method in base_packet has a method that is virtual, what would happen if this method was called in the main method using the base class handle
Now – it is your turn to solve them based on above code starting point and ask more here in comments. We will try and help you with answers if you need!
Good Luck
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