During our recent SystemVerilog Assertions update webinar (http://www.cvcblr.com/blog/?p=802) one of the audience raised a question on how to check asynchronous events using SVA. Here comes a quick response with code. Also simulated using Aldec’s Riviera-PRO tool.
As you can see in the picture, no clock involved per-se, but use the start and end events themselves as clock for the SVA.
So, if you’ve more challenging requirements, do drop in at CVC and we will assist you resolve them!
