Enabling Faster ABV – new initiatives

Assertion Based Verification has certainly been one of the mostly debated topics over the last half-a-decade. So much so that one of the past DVCons was full of SystemVerilog & PSL papers on ABV that someone commented it is “ABV conference” than DVCon (was it DVCon 2005?2006?)

Even then the adoption rate has been slower than expected – agreed by many stats, EDA folks etc. A relatively new EDA vendor is addressing it via some tools, see: http://www.zocalo-tech.com/index.php 

Not clear how easy it will be and how much ROI users will see, but an interesting development I must say.

With SystemVerilog 2009 LRM adding checker constructs we predict that the adoption of OVL-like libraries should dramatically improve. We explained it thoroughly in our SVA handbook 2nd edition, see: http://www.cvcblr.com/blog__resources 

We have a DVCon 2010 paper on this very topic, see: http://dvcon.org/events/eventdetails.aspx?id=108-3 

Let’s see how fast the checker gets implemented by EDA tools, we used VCS for our new book http://www.systemverilog.us/sva_info.html

Hope 2010 brings ABV more and more into RTL engineer’s desktops!

What is there in a number? No, it is not numerology – rather EDA marketing fun!

For those of us who have been following the EDA marketing over several years, it is no surprise that there are dedicated marketing professionals within big EDA companies focussing on conveying message/confusing the ecosystem if needed (unfortunately). We have several anecdotes starting from “VHDL is dead” back in 2003 (http://www.eetimes.eu/uk/17408257) and guess what, last month we had a full-house “Advanced VHDL TB class” (http://www.cvcblr.com/blog/?p=86) and another one being scheduled in Jan 2010. I don’t intend to blame any single entity/individual for this, rather this is how it works, and those of us who have seen it for years understand it. Another classical case was for IEEE-1850 PSL – it is alive and kicking with becoming part of recent VHDL as well. Though not much development on PSL itself, but it is expected to stay for much longer than what some folks have predicted. Need a proof – name an EDA vendor without support for PSL – Mentor, Cadence, Synopsys, Aldec – all have them. It will be foolish to predict that all of these marketing teams went wrong with their predictions – if PSL were to be short-lived why have every EDA vendors invested in it?

Fast-forwarding to present day, recently SystemVerilog VMM 1.2 has been released (http://www.cvcblr.com/blog/?p=91) after a relatively longer incubation/Beta period than usual. And almost instantaneously we find Tom’s analysis at http://tinyurl.com/vmm12-20-ment – True VMM 1.2 has lots and lots of new stuff and even the old features have newer implementations (parameterized versions of channel etc. – maybe they were in VMM 1.1* as well?). But to the user community I believe this is a good thing – we are slowly seeing a sign of convergence to a CBCL becoming reality. Yes today VMM can run on 3 EDA tools and so is OVM. But how well do they interop? Ask Ashsih from Nokia Bangalore, he will tell you the horror stories he had since last 1 year or so.

Recently Accellera VIP-TSC established an inter-op kit, we saw that during recent SVUG here in Bangalore, see: www.svug.org for archives.

More recently (after the SVUG Bangalore event), the VIP-TSC has proposed a new name for this CBCL - “UVM” (No, not URM, rather UVM – fortunately this name has been spared so far by vendors). How this will shape up will be known in coming days, weeks, months if not years!

But it is clear that it will contain contributions from VMM & OVM and hopefully will run on all tools too. Having closely observed both OVM and VMM (1.2 including), there is easier migration path from OVM to VMM 1.2, if needed and vice versa, infact we present that as a handout to out regular training attendees who take up one methodology during training and pick up the other on the go!

With VMM 1.2 (Or 2.0, as per Tom) having similar concepts as OVM the creation of UVM should be lot simpler – we hope. Let’s see.

BTW, there is OVM 2.1 around the corner, should it be re-numbered? Anyone? Vaastu? Numerologists? Mentor is arranging a private Webinar for its valued partners for OVM 2.1 updates, so we should see another blog soon.

To me it is clear that the individual development efforts/bug fixes to both OVM & VMM will continue atleast till UVM 1.0 (??) emerges.By then will we see VMM 1.4? OVM 2.5? Anybody’s guess!

Enough on numbering! Let’s start the convergence, hope 2010 is a luck number for SystemVerilog enthusiasts as UVM should see its birth! Maybe Santa is granting UVM as a gift to SystemVerilog professionals :-)

More on UVM as we hear..

SystemVerilog code automation from Puneet

Good news for all those Emacs + SystemVerilog users. Puneet has just now released his SV Snippet for Emacs, see:

http://coverification.org/2009/12/17/systemverilog-snippets-for-emacs/

Will certainly try it out ASAP. Good start Puneet, keep it up. Thanks for sharing it!

Breakdown of Verification effort – Debug, Debug & more Debug..

Interesting analysis of how Verification effort is being spent across industry:

http://tinyurl.com/dbg-it-man

(See the pie-chart, Figure 2). It goes very much inline with what we have been hearing from customers, competitors and also from our own own experience. So DEBUG is THE area if one were to automate within Functional Verification. I’m little surprised to see a 15% spent on ENV – perhaps it is the case for modern SystemVerilog/VMM/OVM stuff, but again that’s for the initial period I suppose. My belief is if you reuse VIPs, leverage on previous code and hire the right candidate, the ENV creation can be handled within 10% The testcase development is shown as 18%, not clear if some of it spread into the coverage bucket (another 15%) – as there is a strong correlation among the two anyway. I believe this is where technologies like Breker’s trek http://www.cvcblr.com/blog/?p=89 becomes interesting.

 

On the debug – the good old Novas/SpringSoft is still the leader with Siloti, Verdi and Debussy. Though I’m little disappointed at their SystemVerilog solutions – personally I would have liked more innovation on that space from these debug GURUs. They do have “log/transaction display”, but am sure more is in pipeline. A new company http://www.vennsa.com/product.html is showing up at places, will be interesting if anyone locally is using it. It will be worth getting some true success stories to see what exactly it automates.

Staying on the debug – I personally believe lot of these automation originate inhouse at customer sites. For instance during our Ethernet Switch/Router Verification monster, we created several scripts, plots etc. to do intelligent failure analysis (http://www.iec.org/pubs/print/verification_toc.html). Also our recent work with a local SAN customer resulted in visualizing AVL trees from running simulation. See: http://www.cvcblr.com/blog__resources and http://www.snug-universal.org/asia/india09_V1_Abstract.pdf

And then we had this SystemVerilog memory blow-up debug case, http://www.cvcblr.com/blog/?p=29 – so for now Debug continues to fascinate us the most!

Drop me a note if you would like to explore how you can automate your debug challenges.

Happy Debugging!

Formal Verification – Model Checking case study from SUN & Jasper – excellent read, to refer..

 

In case you missed it: http://chipdesignmag.com/display.php?articleId=3723

I mentioned this during our recent Advanced VHDL TB class (http://www.cvcblr.com/blog/?p=86) during PSL session and attendees were very interested. Today I got a mail back from Chandramohan asking for the link, sent to him and read it once again (must admit, not in full indepth PCI-e level). Overall an excellent paper, perhaps a strong candidate for a DVCon Best paper award – real design bugs/scenarios listed..truly worth reading.

Such a nice paper didn’t have to have the following on simulation

Simulation, the alternative, brute force approach, ends up wasting resources and introduces additional risk. Even for cases where you think you understand the full state-space, it requires huge effort to develop a test strategy, e.g. complex test scenario with nested loops etc. Manual effort and test are required. Simulation cycles are long and regression test after modifications is slow. Furthermore, the designer generally has to edit down the simulation and remove certain combinations, without absolute knowledge of whether these are important or not. It is hit-or-miss because no design or verification engineer can enumerate all of these combinations.

With due respect to the authors – they seem to be cornering SIM way too side..One can forget the use of intelligent stimulus generation, adopting functional coverage, sequences, virtual sequences and even better the all new Trek (www.brekersystems.com) – their examples do contain similar PCIe stuff and it is quite powerful too. So let’s not write-off simulation, agreed – if and when formal works it is a great technology, but not at the cost of simulation..

VMM 1.2 is out…finally

OpenSource VMM 1.2 is finally out, see vmmcentral.org – we have been mentioning it to many of our training attendees as “it is coming, it is coming”..now it is HERE!!

 

One of the greatest challenges we face is when our previous SystemVerilog/VMM attendees attend our newer classes (for upgrade, learn other methodology etc.) – they get very confused about the VMM channel (old way) vs. the new TLM way. The put/get definitions were simple, elegant, ready to use for first timers in VMM 1.0*. True the TLM adds lot of value, but existing users are finding it hard..This is where we folks like CVC fit in I suppose, so no complaints..

 

Enjoy and welcome the TLM way!

VMMing of a VHDL-C based Environment, anyone?

Recently @VGuild Mike asked”

 

Does anyone use ModelSim's FLI for verification? What are the pros and cons of this?
I've been considering adopting SystemVerilog for writing test environments (we code our designs in VHDL and use PSL for assertions and functional coverage) but, from what I can gather, instead of SV I might as well just use ModelSim's FLI and write sophisticated testbenches in C. As an engineer, I am already very familiar with C, and so learning another language for verification (SV) is not desirable.
I suppose SV is more portable to other tools, rather than relying on ModelSim's FLI. And I suppose SV is supported by frameworks such as OVM. Other than that, why not use C/C++ as your verification language with the FLI?

Though the entire EDA marketing machinery is strongly biased on SystemVerilog, let’s realize that there is a sizeable population using VHDL, C etc. Few pointers for those unconvinced:

• Our recent VHLD Advanced TB attendance here in Bangalore (http://www.cvcblr.com/blog/?p=86).
• Continued interest from our customers on FPGA Verification courses: http://www.cvcblr.com/blog/?p=60 
• VHDL random generation, recent webinar @ aldec.com

So what’s the solution for VHDL users, looking at high-end Verification stuff? Is SystemVerilog THE only way? We at CVC believe SystemVerilog is “A way”, not necessarily THE ONLY way. For instance PSL becoming part of VHDL makes it a string candidate than SVA for VHDL users (yes even with recent SVA-09 features included http://www.systemverilog.us/sva_info.html, PSL’s LTL is long proven, well supported than SVA-09). I hear recently more momentum towards PSL from local VHDL users.

So coming back to Mike’s topic – few suggestions:

• No single-size fit all solution
• FLI is a choice if for foreseeable future Modelsim is bought over by your employer. But if there is any question of portability (given that there are strong contenders, pricing factor – did we not hear of BIG EDA vendor slashing prices like crazy – much like Magma style, but for verification?
• I highly recommend to look at VHPI than FLI as it is IEEE standard and well supported by tools like VCSMX, IUS, Aldec (Riviera for sure, Active-HDL too I guess, anyone to confirm??)
• For SystemVerilog like features – explore www.trusster.com for TEAL/TRUSS – akin to VMM/OVM without all bells and whistles, but provides a baseline and is FREE!! Can even run with Icarus for Verilog, hurray!!

So choose the right tool for the right job..

Breker’s Trek @DAC and CVC’s engagement so far..

Another piece partly covered in Cooley’s report, but for those interested in full details (more technical updates coming in soon)..

Here are my (and my team, who is looking at it closely during an eval) observations on Breker's Trek tool. What we really like about this tool is that it an add-on to any existing methodology/environment (atleast we look at Verilog, SystemVerilog, VMM & OVM for now). Their marketing is also quite good in saying we solve the last 20% of the problem (which usually is the pain-point) though it needs to be proven (our eval is still in early stage). The BNF syntax looks interesting and for the uninitiated it may take a while, but certainly no big deal. We can appreciate the value such a tool brings in for testcase generation. However they claim to be eliminating the need for complex checkers - this is something we are still wary about and would like to delve deep into during the eval. In our view the checker part is hard and will be hard even with Trek. Our view of this feature of Trek is it is an ability to correlate the testcase and coverage to the checking mechanism - hopefully at a higher level of abstraction. If this can be achieved we would be glad with that. The coverage results annotation and reachability analysis part is really promising as it presents the test-coverage at a higher level of abstraction than traditional SV. In SV world one needs to code the complex covergroups, code/generate tests, correlate them and then view lower level coverage data (GUI/HTML/TEXT) to extract same kind of information.

Thanks

Shalini, CVC Pvt Ltd

Our NuSym updates from DAC and around..

Some of you might have seen our report of DAC from John Cooley. Here is our full version of NuSym report for those interested. Trek to follow (wiht more updates after the DAC report was sent out)..

We at CVC have been tracking Nusym's technology for a while. I visited their booth & demo and here are our (mine combined with my CTO's inputs) comments/impressions. While the generation of additional tests/filling holes is a critical piece of its features, I believe the coverage analysis feature is not so well published/well understood.

With our customers who are serious about coverage, the analysis of coverage holes has been one of the biggest pains. The sad part is no major EDA vendor is really adding features to enhance that, with Nusym addressing that problem, it is certainly very useful. The techniques they showed in their slides/demo are not truly path breaking but simple ones that can aid in not wasting time with unreachable coverage holes. It is that simplicity that made me very interested in their stuff. But it is unclear if the tool can go beyond the "static analysis" part and offer more sophisticated means to analyze/exclude coverage holes.

While the major EDA vendors claim to address this challenge, much is yet to be done with say minor changes to RTL, then the whole analysis goes invalid and has to be repeated - much manually. It will be great if Nusym can address that.

The other not-so-much-spoken feature is their "replay" technique - perhaps it is still maturing, but sure enough it is one of those very useful techniques in regression runs.

Thanks and Regards,

Shalini Pandey

CVC Pvt Ltd

What are your painpoints with SystemVerilog ABV adoption?

While there is so much talk about ABV in the market, the adoption is still far less than desired/expected by the buzz! Harry Foster from Mentor tries to find some rationale in his new blog at:

http://blogs.mentor.com/verificationhorizons/blog/2009/12/06/abv-and-people-from-missouri/#comment-6

 

Here is what we from CVC feel about it (also added as comments in that blog).

>> What are the obstacles you see to adoption?

Major one I hear from RTL folks often is the verbosity associated (as of SystemVerilog 2005) with using OVL-like libraries. Especially existing users of 0-in checkerware are so much pampered by the ease of use and the value it adds - though their management may have the extra $$ as concern - it is hard for them to appreciate the need to type-type-type the “clock, reset” mundane stuff! It was all being “inferred” so far and suddenly come a standard language/implementation such as SVA and that takes them back in history! Refer to AMD’s excellent presentation on OVL TC for a proof! True, the new (very new I must say) “checker” construct along with $inferred* takes care of it (sigh… it lacks $inferred_enable). We cover these in our recently published SVA Handbook 2nd edition (http://www.systemverilog.us/sva_info.html) and also in upcoming DVCon 2010 paper.

Cheers
Srini
http://www.cvcblr.com

 

What do you have to say? Please comment, your views will hopefully help in shaping up future SystemVerilog standard!

Adv VHDL Testbench training - Aldec-South Asia begins with a BANG!

For those who missed it, see:

http://www.aldec.in/Company/News.aspx?newsid=34678573-19e6-45a3-99d5-9d5b6accda6c 

This is a significant move I would say as it reinforces few facts:

• Industry is slowly recovering (Hurray!!)
• India/SouthAsia is gaining more and more importance as a wide customer base – apart from major EDA vendors, others are setting up their own centres, driving investments etc.
• India as such provides a vibrant FPGA market and there is enough to tap onto it for EDA vendors!

Recently Aldec-SA conducted a 2-day seminar on “Creating efficient Testbenches using VHDL”. CVC did the delivery of this seminar, being VHDL & Verification experts.

 

We got very good feedback from this event, here is a sample:

**** Straight from customer ************

  Hello Sir,

I am Ramesh R Nair, working in Continental Automotive as an ASIC verification engineer as part of my internship programme of M.Tech(VLSI).

I have attended your  training class on test bench writing last week(ALDEC).

Although we are writing a lot of test benches some utilities were unnoticed.. you bring those things to light.

So it  was very helpful and i shared it with my team members.

Thank you and Congratulations.

Best Regards

Ramesh R Nair

Continental Automotive Components

Bangalore

*****************************

It is always great to hear feedback from customers and it gets better if it is a positive one :-)

What’s wrong with the present ABV promotion?

If you have not heard of the buzz word “ABV” (and assuming you are a VLSI front-end engineer of-course) you must be living in a different world I must say (no pun intended) – with so much marketing around it is hard to have missed it – with SystemVerilog Assertions, PSL, OVL etc.

Despite that there are some folks who say the adoption is not as much as predicted – heard it from Adam Sherer earlier this week here in Bangalore and now read it on: http://www.edadesignline.com/showArticle.jhtml?articleID=221901260 

 

Well I for one don’t believe this is fully true – atleast in India/AsiaPac – CVC has done well with ABV, we have developed PSL based MIP (Monitor IP) for Taiwan customers, got paid, and delivered several customer trainings on it etc. Though the recent focus has been more on OVM/VMM/VSV – SVA is still making money I must say. It is entering FPGA domain well, see recent ModelsimDE release, Active-HDL supporting ABV for long time now for FPGA domain etc. And just today we introduced PSL to a large customer base (VHDL house) and it is well received among engineers.

 

But – yet I agree to some extent, there are challenges with it – that prevents it becoming “Mainstream”. For one we don’t have good tool support to verify Assertions standalone. There were early starts with “Assertion Studio” http://www.systemverilog.org/pdf/AT_HDL_Symposium.pdf but it is no longer to be found! This is to say – I don’t have RTL, no TB, just write SVA/PSL – can I visualize/verify them standalone? Formal tools can in principle do it, I have seen it with Magellan whilst at SNPS, but internally. Not sure if IFV can do it, Jasper can do it etc. Even if they do – it is too expensive an option I guess!

Secondly – I believe there is a lack of good “reference” – to common “templates”. We tried addressing it in our SVA book via dictionary, but being a big book not sure how many used that part of the book. Didn’t hear much from customers on that.

 

While doing trainings I always felt this would be a perfect fit for an animation based demo/training, tried prototyping it with a publishing house, effort dried off due to lack of commitments/funds. Also – all said and done, the language features as they exist are INADEQUATE to express temporal behaviors intuitively. This is even with SVA-09 features. If I were to re-design a language for it (read it as: if I had all the time and money needed for it) I would develop a from-scratch, user driven means for it, than language/tool imposed restrictions dominating the definition. Just a sample:

“Variable delays” are not allowed in SystemVerilog Assertions – give me a break…(No I don;t need a work-around, I can send you if needed, drop me an email).

Sub $5000 high-end Mixed HDL simulator - VHDL+Verilog+SV-Design

 

http://edageek.com/2009/11/16/vhdl-verilog-xilinx-secureip/

Not a bad news after all – given that the industry is showing signs of recovery, such offerings are GREAT indeed – during the downturn several mergers, IP accumulation, consolidation have happened. That might have led to mix of languages in new SoCs. Usually the cost of ownership of a full fledged Mixed-HDL simulator (from any of 3 big EDA vendor) costs a lot (some say a “fortune” though I disagree). But this Riviera offering is certainly encouraging indeed.

But is this a “sign-off” tool? Anyone?

And BTW – in DAC they announced $1995 package for Active-HDL with similar support, so it is real!

http://www.aldec.com/Company/News.aspx?newsid=c86c2ee8-5490-4eae-b61e-a7c0aaf7396c

Sub $5000 high-end Mixed HDL simulator - VHDL+Verilog+SV-Design

 

http://edageek.com/2009/11/16/vhdl-verilog-xilinx-secureip/

Not a bad news after all – given that the industry is showing signs of recovery, such offerings are GREAT indeed – during the downturn several mergers, IP accumulation, consolidation have happened. That might have led to mix of languages in new SoCs. Usually the cost of ownership of a full fledged Mixed-HDL simulator (from any of 3 big EDA vendor) costs a lot (some say a “fortune” though I disagree). But this Riviera offering is certainly encouraging indeed.

But is this a “sign-off” tool? Anyone?

Hardware Emulation becoming more and more affordable

Read: http://www.your-story.org/eve%E2%80%99s-latest-emulator-offers-the-lowest-cost-of-ownership-in-the-industry-62042/

 

With the so called “penny-per-gate” pricing – sure is a marketing gimmick, it is becoming more and more viable to explore low cost emulation stuff. We still see that our customers continue to rely on own, self cooked FPGA boards, but with such innovative business models it may be changing soon..

 

Good job Eve folks – I wonder if they allow sharing “across customers” – say we host one Zebu server at CVC and allow several customers to log-in and pay-per-use!