For those of us who have been following the EDA marketing over several years, it is no surprise that there are dedicated marketing professionals within big EDA companies focussing on conveying message/confusing the ecosystem if needed (unfortunately). We have several anecdotes starting from “VHDL is dead” back in 2003 (http://www.eetimes.eu/uk/17408257) and guess what, last month we had a full-house “Advanced VHDL TB class” (http://www.cvcblr.com/blog/?p=86) and another one being scheduled in Jan 2010. I don’t intend to blame any single entity/individual for this, rather this is how it works, and those of us who have seen it for years understand it. Another classical case was for IEEE-1850 PSL – it is alive and kicking with becoming part of recent VHDL as well. Though not much development on PSL itself, but it is expected to stay for much longer than what some folks have predicted. Need a proof – name an EDA vendor without support for PSL – Mentor, Cadence, Synopsys, Aldec – all have them. It will be foolish to predict that all of these marketing teams went wrong with their predictions – if PSL were to be short-lived why have every EDA vendors invested in it?
Fast-forwarding to present day, recently SystemVerilog VMM 1.2 has been released (http://www.cvcblr.com/blog/?p=91) after a relatively longer incubation/Beta period than usual. And almost instantaneously we find Tom’s analysis at http://tinyurl.com/vmm12-20-ment – True VMM 1.2 has lots and lots of new stuff and even the old features have newer implementations (parameterized versions of channel etc. – maybe they were in VMM 1.1* as well?). But to the user community I believe this is a good thing – we are slowly seeing a sign of convergence to a CBCL becoming reality. Yes today VMM can run on 3 EDA tools and so is OVM. But how well do they interop? Ask Ashsih from Nokia Bangalore, he will tell you the horror stories he had since last 1 year or so.
Recently Accellera VIP-TSC established an inter-op kit, we saw that during recent SVUG here in Bangalore, see: www.svug.org for archives.
More recently (after the SVUG Bangalore event), the VIP-TSC has proposed a new name for this CBCL - “UVM” (No, not URM, rather UVM – fortunately this name has been spared so far by vendors). How this will shape up will be known in coming days, weeks, months if not years!
But it is clear that it will contain contributions from VMM & OVM and hopefully will run on all tools too. Having closely observed both OVM and VMM (1.2 including), there is easier migration path from OVM to VMM 1.2, if needed and vice versa, infact we present that as a handout to out regular training attendees who take up one methodology during training and pick up the other on the go!
With VMM 1.2 (Or 2.0, as per Tom) having similar concepts as OVM the creation of UVM should be lot simpler – we hope. Let’s see.
BTW, there is OVM 2.1 around the corner, should it be re-numbered? Anyone? Vaastu? Numerologists? Mentor is arranging a private Webinar for its valued partners for OVM 2.1 updates, so we should see another blog soon.
To me it is clear that the individual development efforts/bug fixes to both OVM & VMM will continue atleast till UVM 1.0 (??) emerges.By then will we see VMM 1.4? OVM 2.5? Anybody’s guess!
Enough on numbering! Let’s start the convergence, hope 2010 is a luck number for SystemVerilog enthusiasts as UVM should see its birth! Maybe Santa is granting UVM as a gift to SystemVerilog professionals :-)
More on UVM as we hear..
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