What’s wrong with the present ABV promotion?

If you have not heard of the buzz word “ABV” (and assuming you are a VLSI front-end engineer of-course) you must be living in a different world I must say (no pun intended) – with so much marketing around it is hard to have missed it – with SystemVerilog Assertions, PSL, OVL etc.

Despite that there are some folks who say the adoption is not as much as predicted – heard it from Adam Sherer earlier this week here in Bangalore and now read it on: http://www.edadesignline.com/showArticle.jhtml?articleID=221901260 

 

Well I for one don’t believe this is fully true – atleast in India/AsiaPac – CVC has done well with ABV, we have developed PSL based MIP (Monitor IP) for Taiwan customers, got paid, and delivered several customer trainings on it etc. Though the recent focus has been more on OVM/VMM/VSV – SVA is still making money I must say. It is entering FPGA domain well, see recent ModelsimDE release, Active-HDL supporting ABV for long time now for FPGA domain etc. And just today we introduced PSL to a large customer base (VHDL house) and it is well received among engineers.

 

But – yet I agree to some extent, there are challenges with it – that prevents it becoming “Mainstream”. For one we don’t have good tool support to verify Assertions standalone. There were early starts with “Assertion Studio” http://www.systemverilog.org/pdf/AT_HDL_Symposium.pdf but it is no longer to be found! This is to say – I don’t have RTL, no TB, just write SVA/PSL – can I visualize/verify them standalone? Formal tools can in principle do it, I have seen it with Magellan whilst at SNPS, but internally. Not sure if IFV can do it, Jasper can do it etc. Even if they do – it is too expensive an option I guess!

Secondly – I believe there is a lack of good “reference” – to common “templates”. We tried addressing it in our SVA book via dictionary, but being a big book not sure how many used that part of the book. Didn’t hear much from customers on that.

 

While doing trainings I always felt this would be a perfect fit for an animation based demo/training, tried prototyping it with a publishing house, effort dried off due to lack of commitments/funds. Also – all said and done, the language features as they exist are INADEQUATE to express temporal behaviors intuitively. This is even with SVA-09 features. If I were to re-design a language for it (read it as: if I had all the time and money needed for it) I would develop a from-scratch, user driven means for it, than language/tool imposed restrictions dominating the definition. Just a sample:

“Variable delays” are not allowed in SystemVerilog Assertions – give me a break…(No I don;t need a work-around, I can send you if needed, drop me an email).