TeamCVC (http://in.linkedin.com/in/cvcblr) is at Cochin, a famous port-city in South India (http://en.wikipedia.org/wiki/Kochi) this week on a “Mission SystemVerilog” at a customer site. It is a 4-day program covering:
- SystemVerilog basics for RTL designers (http://www.cvcblr.com/trng_profiles/CVC_LG_SVD_profile.pdf)
- System Verilog Assertions (http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf)
- SystemVerilog for Verification engineers (VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf)
The audience is a mix of young, enthusiastic engineers in their early-to-mid career – all very keen to hone their skills on SystemVerilog. Our CTO, Srini (http://in.linkedin.com/in/svenka3) chose to customize the training in a timely manner to get the audience involved and interactive. During Day-2, it was a true “field-day of SystemVerilog Assertions”. Especially when it came to Sequence repetition operators, it was fun all across the room. Needless to say CVC’s SystemVerilog Assertions labs are very well laid out with concrete examples to demonstrate the various sequence operators. However with assertions the fun really lies when you “slightly” change the sequence and/or the trace. Here are some screenshots from this “field-day”.
One of the sequences that we experimented is to demonstrate the difference bet’n non-consecutive [= N] & GOTO [-> N] operator.
One of their smart engineers asked/wanted to change the ##1 to ##0. This is to explain the “endpoint” of a sequence/property as in:
a |=> b [-> 2] ##1 c;
Lucky that we had access to Riviera-Pro running on our laptop, on-the-fly we could tweak the code/trace and demo it live:
The fun gets only more when there are multiple threads & multiple attempts. Here is how Riviera-Pro nicely shows it up on Waveform – like a real “THREAD”.
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