SystemVerilog for Verification: Explore technologies for “Verification Closure” at DVCon BoF meeting, Tuesday Mar 1st 6.30 PM (PST)

Big picture – Verification Closure

Panel members: Cadence, NextOp, Breker & CVC

If you are attending DVCon starting tomorrow, here is a panel that you may not want to skip – yes UVM is hot and ready-to-go. How do we leverage that and get to faster Verification Closure – that’s precisely what we will be discussing in this “Birds-of-a-Feather” panel at DVCon www.dvcon.org on Tuesday Mar 1st, 6.30 PM US/Pacific time at Donner Ballroom, DoubleTree Hotel, San Jose.

Here is a summary of what to expect in this panel discussion:

UVM is great! Enables interoperable VIPs to be created, reused. In a typical SoC – several such UVM VIPs get integrated and 1 (or more) embedded processors (ARM-like) configure/control the flow. Individual sequences/virtual sequences at UVM level will do great for peripheral-alone testing.

Taking right from UVM SoC reference flow @ www.uvmworld.org, here is a sample SOC:

How about true “flow/scenario” testing? UVM’s virtual sequencer is “A possibility”. A pragmatic approach as outlined by an excellent article by my good friends @ Applied Micro, Pune (India) is here:

http://www.design-reuse.com/articles/22264/system-verilog-ovm-verification-reusability.html

The above approach requires lot of coding, synchronization and pretty much directed across transactions/interfaces. How do we randomize “across interfaces/peripherals” to mimic system-level flows/scenarios?

Even if we code up all Sequence libraries, virtual sequences and virtual sequencers – we got only the stimulus, what about complete “Verification Closure”?

On top, overlay Low Power features, requirements and annotate Power State table information – the number of different paths/arcs to be coded and tested is mind boggling – imagine coding them via virtual sequences/sequencer – do-able, but lot of work indeed!

Every DV team does this today in one-way or the-other. But what new technologies are available or becoming available to assist?

Come and listen to experts in this domain at “Birds-of-a-Feather” panel at DVCon www.dvcon.org on Tuesday Mar 1st, 6.30 PM US/Pacific time at Donner Ballroom, DoubleTree Hotel, San Jose.

Here are some key items that would be discussed: If you have more ideas/questions send them across to sevnka3@gmail.com or post as additional comments here at www.cvcblr.com/blog I will incorporate them as much as I can!

Need truly inter-operable VIPs to start with – This is where UVM comes-in. We at CVC are at DVCOn UVM poster session.
Need key “metrics” to define, drive and track the progress (Various sources including formal)
How to focus on “critical, high quality” coverage targets?
A coherent, high-level mechanism to capture the scenario models that aid in: