Friday, January 21, 2011

TechnoFun with System Verilog – I turned rand_mode OFF, yet get constraint violation? Crazy Friday evening phenomenon, maybe?

clip_image002Ravi Teja , ASIC Design-Verification Engineer @ www.cvcblr.com &

image  TeamCVC (Nikhil, Satish, Srini et al.)

SystemVerilog is a massive language with several surprises under its belt. Every time you encounter some unexpected result, the first reaction is “Oh! I know System Verilog, this is incorrect behavior of the tool”. Voila! EDA developers get paid *really well* and read the LRM thoroughly before committing their code in. This is not to say that there are no bugs in EDA tools (“bug free EDA tool” is more or less an OXYMORON). But with System Verilog tools becoming more and more stable and advanced, it is very likely the case that you fall under the famous John Cooley’s signature (www.deepchip.com):

 image

So was our recent experience with Aldec’s Riviera-Pro simulator with SystemVerilog constraints. 

Let the code speak for itself:

class xactn;
   rand int var1;
   rand int var2;
   constraint c_var1 { var1 inside {[1:10]};}
   constraint c_var2 { var2 inside {[1:10]};}
endclass:xactn

Now var1 & var2 are non-state variables. Whenever I randomize an object of this class, the solver should obey the constraints – no ground breaking stuff, is it? Consider turning the non-state variables to “inactive” state. SystemVerilog supports rand_mode(0/1) for this, a quick explanation for the same is below:

image

 

Now the real fun starts when you delve into corner cases (a la “the devil lies in the detail”). Even though the rand variable is turned inactive, its value MUST be within the values as demanded by the constraints – in other words the “constraints” are still ACTIVE. This has obvious but overlooked results when used with a rand_mode(ON/OFF). The results after randomization are tabulated below:

Picture1

So why is the 2nd & 3rd case don’t result in random values for var2, var1 respectively? Isn’t that a bug in the EDA tool? Shouldn’t we be calling their support@aldec.com staff? Hold on.. Let’s believe the tool, after all – some of the best minds in comp-science write these geeky solvers, they must have had something in their mind while writing this piece of code inside :-)

A little bit of RTFM (Read The Fine Manual) reveals the “hidden” secrets of “Art of Debug” with Riviera-Pro. It supports a rc_verbose flag which, when set to a magic value of “2” throws out messages to the log file.

set rc_verbose 2

# RCKERNEL: Error: ../src/test.sv(1): The condition 'c_var1()&&c_var2()&&rc_ext_constraint' is overconstrained.

# KERNEL: 1 (0,0) Var1 =           0 , Var2 =           0

# RCKERNEL: Error: ../src/test.sv(1): The condition 'c_var1()&&c_var2()&&rc_ext_constraint' is overconstrained.

# KERNEL: 2 (0,1) Var1 =           0 , Var2 =           0

# RCKERNEL: Error: ../src/test.sv(1): The condition 'c_var1()&&c_var2()&&rc_ext_constraint' is overconstrained.

# KERNEL: 3 (1,0) Var1 =           0 , Var2 =           0

# KERNEL: 4 (1,1) Var1 =           3 , Var2 =           9

# KERNEL: 5 (0,0) Var1 =           3 , Var2 =           9

# KERNEL: 6 (0,1) Var1 =           3 , Var2 =           4

So the first 3 randomize() calls were failing – important that you handle the return value from object.randomize() (Guideline-1).

First three cases gave a constraint violation. We observed that for cases 1,2,3 atleast one of the constraints is not fulfilled.Hence the randomize method returns zero. What? I turned the rand_mode to OFF, yet it tries randomizing and failing? Crazy Friday Phenomenon Huh?

 

Oh Dear, wait..let’s peel the onion and see why..

Picture1

This is because each call to randomize involves two steps:
1)solve
    In this step all the constraints are solved (as they are still active). The solver must keep the values of var1 and var2 
between 1 to 10. Their default values are however 0. (i.e var1=0 & var2=0) . This violates the constraints, hence the solver failed.
2)assign
If the solver passed (i.e no constraint violation) and rand_mode is ON then the randomized value is assigned to the variables

Now in case 2 & 3 wherein only one of the variables is set to rand_mode(OFF), the AND operation means that – since the solver ahs failed, no assignment of potential random value to the other variable is performed, hence retaining the value 0f “0”.

Now, the constraint debugger with Riviera-Pro is good to start with, wish it had pin-pointed it to the exact constraint that caused the violation, instead of combining both into single equation as:

# RCKERNEL: Error: ../src/test.sv(1): The condition 'c_var1()&&c_var2()&&rc_ext_constraint' is overconstrained.

Oh, let’s leave some room for improvement :-)

Now, as a closing remark and 2nd coding guideline – if you are changing the rand_mode, see if you can isolate related constraint on that variable and make constraint_mode(OFF) as well. Once again as John Colley puts it:

 image

Sunday, January 16, 2011

From a fresh grad to VLSI Design engineer – Meet Mr. Kaleem, Sasken

 

They say the best appreciation one can get is through one’s customers’ voice – we at CVC (www.cvcblr.com) take every individual trainee as serious as our corporate customers. That has been our reason behind success on both Corporate & individual levels. Here is yet another success story, this time from Md. Kaleem, ASIC Design-Verification Engineer @ Sasken. Kaleem got trained by TeamCVC and also was consulting for us for 2 projects after the training, through which he gained real practical knowledge that has helped him sail through the tough job climate. Kaleem went through our EIC (http://www.cvcblr.com/trng_profiles/CVC_EIC_profile.pdf) and then worked on OVM http://www.cvcblr.com/trng_profiles/CVC_DR_OVM_profile.pdf projects before moving on to even better job prospects.

Here is what he wrote to us over this weekend! Good luck Kaleem and keep in touch!

Mohammed Kaleemulla (http://in.linkedin.com/pub/mohammed-kaleemulla/23/186/b98)

Sent: Sunday, January 16, 2011 12:23 PM

Hi,

Sir This is Kaleem here,i have got a job in Sasken for the post of design verification engineer,I thank CVC for giving me all the support required for developing  the technical and knowledge-able skills, without which I wouldn't have  reached here and I hope we will have a reciprocate communication.


Regards
Kaleem

SystemVerilog constraints – distribution & using FCOV to visualize the effect

– Satish U, ASIC Design & Verification engineer @ CVC (www.cvcblr.com)

SatishU_CVC Every day at work is learning something new. More so when you are asked to work deep into advanced technologies such as SystemVerilog. In a recent project I was asked to delve deep into the constraints portion of SystemVerilog and solve few customer problems in modeling real life traffic pattern generation using SystemVerilog constraints. As part of it, I came up with an interesting to way to visualize the distribution through SystemVerilog covergroup/coverpoint. Though it is little round-about and may not be the best way to “verify” distribution, the technical lead at CVC quickly grasped the value and encouraged to explore more and develop a blog on the same. It is this “cultivating ideas” that makes working at CVC (www.cvcblr.com) a perfect blend of learning & fun (and don’t miss it – very aggressive timelines too).

 

                  A New way to check the distribution

  By definition the distribution within randc must be uniform. Let’s formulate this statement and validate the same. To find the distribution of lets say randc within a particular range N (N is the number of values in the range). Now let us assume M is the number of times an object is randomized.

Each value has a probability of 1/N.
 

  • Case1: IF M = 1*N - If M= N then the values should be unique without any repetition.
  • Case2: If M = 2*N - each value should be generated 2 times.
  • Case3: M = K*N. Hence the number of times each value shall be generated is equal to K.

The N & M determine the “stimulus” side of verification. How do you “check” the distribution? An automated & robust method would be to use a queue and check the contents of the queue to see if they are unique, Infact one of our interns (Suhas: http://in.linkedin.com/pub/suhas-reddy/15/b02/49) is doing this as a mini-project at CVC (www.cvcblr.com) as part of our popular BUDS internship (http://www.cvcblr.com/downloads/BUDs_CVC_Acad.pdf).

However I proposed another interesting way to do this: Declare X as a cover point within a covergroup , so by default we will have N bins created for the N number of values (else one could use the auto_bin_max if care to). Other choice would be to use an array bin as shown below.

To demonstrate with an example:

`define N 4

`define K 1
`define M `K ** `N

`define seed_value 100

package pkg;
class xactn;
  randc bit [(`N-1):0] a;

  covergroup cg;
   A_cp      : coverpoint  a { bins a[] =  {[0:15]};}
  endgroup:cg
   function void post_randomize;
     cg.sample();
   endfunction

lets assume a 4 bit vector a, So we can have 16 possible values (N = 16).

We used Aldec’s (www.aldec.com) Riviera-Pro:       Rvra-Pro

Here is how Riviera visualizes it in its coverage report.

Riviera
 

  • Case1: for M = N if all the bins are hit once it means that i have uniform distribution.
  • Case2: M = 2 * N - each bin should be hit 2 times.
  • Case3: Now lets take the constant 2 as K. the equation becomes M = K*N. Hence the number of times each bin is hit will
       be equal to K.

We used this method to analyze various constraints and distributions. More about it in part-2 of this blog. Stay tuned to VoW blog