Debug SystemVerilog code the right way with Verdi

Srinivasan Venkataramanan, CVC Pvt. Ltd. www.cvcblr.com

Sreenath V, CVC Pvt. Ltd. www.cvcblr.com

One of the many challenges in taking over a block developed by others is the quick ability to grasp the big picture fast and then delve deep into some focus areas. Talking of SystemVerilog based Verification code base (say with a base class such as VMM) is even more challenging as many engineers still find it new. During recent reviews at customer sites we often find engineers asking questions like:

1. How do I quickly know the various transactors in my environment? Of-course one can go through UNIX find-grep route, but with modern verification base, there has to be a modern approach to this ever lasting challenge as well.

2. With several macros being used to reduce the verbosity in coding, the reading/deciphering the code by a novice engineers becomes more challenging. If tools don’t address this part, it is possible that the benefits of code shrink by these macros may get quickly lost with the time being spent by a new engineer trying to understand it in detail.

SpringSoft’s Verdi (tm) has solid support for SystemVerilog testbenches with a full fledged Testbench browser, macro expander etc. It also provides a nice transaction debug capabilities, more on that on a separate blog soon.

What is nice about Verdi is the ability to get a quick view of inheritance structure via its Testbench Browser. See below for an example (look at the Green eclipse area). It is very easy to note the transactors derived from a base class such as vmm_xactor.

 

On the second challenge, Verdi makes it very convenient to expand/collapse a macro.

1. Select the macro usage on the source window.

2. Press “Control-m” – expand macro; See below for a screenshot, l

3. The source window now has an expand/collapse icon (+/- symbol) to the left of the macro line.  (Green eclipse below)

4. When you expand, the “behind the scene” code gets colored on w white background quickly making it distinguished from rest of the code. ((Green rectangle below).

 

We recently had a customer asking for all VMM component code expanded, and it was merely a 15 minute job with this tiny little feature to get that done!

Happy debugging!

Early validation of RTL – with no Testbench!

 

Srinivasan Venkataramanan, CVC Pvt. Ltd.

Looks like Jasper DA (www.jasper-da.com) is on a mission to drive simulation a passé J On a more serious note, their recently announced ActiveDesign (TM) technology sounds pretty interesting for early RTL validation. Before I hear that “Aha..that’s my favourite LINTing”, hold on.. this is much more than that – one can see real waveforms– no testbench is ready yet, but the tool can create quality waveforms for you!

Sounds too good to be true, well their demo indeed shows a very representative real life design – AHB-lite to AXI bridge with 4 AHB-lite masters.

I had a chat with the ActiveDesign team recently to understand what goes “behind-the-scene” (Norris Ip, Holly Stump & Saptarshi all from Jasper). My main doubt on this “early RTL validation” was whether it can work for custom protocols and whether user needs to provide some assertions to get this working. These questions are relevant because we at CVC have prototyped similar stuff for standard protocols via our SVA/PSL based MIPs (Monitor IPs) and some commercially available tool features from other EDA vendors – it involves few hacks and scripting, but doable – if put in some hard work. It requires either an advanced SVA/PSL aware simulator or a model checker/formal tool.

Coming back to Jasper, the short & sweet answer is:

“No, user doesn’t have to create any assertions for getting this. The tool analyzes the RTL code and , based on a few user-interactions with the GUI, waveforms are created". And yes it does work for any design not just for standard protocols” As a side note the tool can create SVA code for the “behaviors/recipes” – more on it later.

The technology is built around Jasper’s popular and proven Visualize (TM) and recently announced “Behavioral Indexing (TM)”. More on the “behavioral indexing” in one of my next entries.

For now, if you are developing a fresh RTL and want to validate it without having to wait for RTL to finish, TB to be ready etc. look at ActiveDesign. Of-course I also highly recommend running LINT before you do that, though Jasper doesn’t have that in this platform. You may want to try some of the new linters such as Aldec’s ALINT, see: http://www.cvcblr.com/blog/?p=99 for a fresh look at Linters.

Signs of maturity in EDA tool built-in examples

During a recent look at ActiveDesign product from Jasper (http://www.jasper-da.com/products/ActiveDesign.htm), I was pleasantly surprised to see a high quality design being used as the case study. Usually such early product demos contain tightly canned examples, showing only the relevant tool features and much less on the actual design. Here is a refresher – we get a very representative real life design – AHB-lite to AXI bridge with 4 AHB-lite masters, a refreshing change in EDA space.

See below for a screenshot of the demo design:

Tool demos are not on dummy designs, becoming more and more realistic indeed!

On a similar note, Breker’s Trek (www.brekersystems.com) has $TREK_HOME/examples that are complete SoC level test synthesis – not just “Hello World”, “foo-bar” anymore! Other interesting designs include a Cache controller model, CPU etc.

Similar is the SoC kit initiative from Cadence (www.cadence.com/products/fv/iv_kit) – this one tops the list of all EDA demos I’ve seen in years on Verification – they started back in late 2007 and have been growing in strength over years. During CDNLive 09 @ Bangalore, CDN showed their roadmap for these kits and clear indications are that these will be extended to ESL platforms too.

Sure all vendors ship more and more examples with their tools nowadays, this also means they employ/engage with real verification engineers besides R&D, support engineers, good for the job market, hopefully :-)

SystemVerilog covergroup – bins and the value set matching

During our last week Verification with SystemVerilog class (VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ), an interesting question popped up during functional coverage session. As user defined bins are created for vectors in SystemVerilog, what if the value set range is not divisible by the specified number of bins (say in a fixed number of bins case)? 

Consider:

[cpp]

bit [4:0] vec_5bits;

covergroup cg;

  cp1 : coverpoint vec_5bits {

    bins four_buckets [4] = {[0:$]};

    bins five_buckets [5] = {[0:$]};

  bins fifty_buckets [50] = {[0:$]};

}

endgroup : cg

[/cpp]

Let’s analyze the above:

four_buckets –> simple, each contains 8 values, uniform

five_buckets –> 5 buckets, first 4 will have 6 values each, 5th bucket will contain all the remaining 8 values:

              [0,1,2,3,4,5], [6,7,8,9,10,11], [12..17], [18..23], [24,25,26,27,28,29,30,31]

fifty_bukcets –> first 32 bins will have 1 value each, remaining 18 shall remain empty!!

Questa prints a nice warning about the last case as below:

VSIM 1> run 990
# ** Warning: (vsim-8546) The number of values specified '32' is less than the size '50' of fixed-size array bin 'fifty_buckets' in Coverpoint 'cp_1' of Covergroup instance '\/top/spram_fcov_1/my_cg_0 '. The '18' empty bins will not contribute towards coverage.

Debug SystemVerilog macros with VCS-DVE

Srinivasan Venkataramanan, CVC Pvt. Ltd.

Rashmi Talanki, Sasken

John Paul Hirudayasamy, Synopsys

An extract from a little lengthier post @ http://www.vmmcentral.org/vmartialarts/?p=922 – focus here only on Debug side on this post:

One of the powerful features of SystemVerilog is the ability to create TEXT macros (those `define s) with arguments – they can create fairly complex code in jiffy. Take a look at VMM source code if you need examples.

In a recent customer engagement, we had to dig deep into VMM atomic Generator code that gets created by the one liner macros!

During the coding work, the customer opened up vmm.sv and got trapped in the multitude of `define vmm_atomic_gen_* macros with all those nice looking “ \ “ at the end – thanks to SV’s style of creating macros with arguments. Though powerful, it is not the easiest one to read and decipher – again for a first time SV/VMM user.

Now comes the rescue in terms of well proven DVE – the VCS’s robust GUI front end. Its macro expansion feature that works as cleanly as it can get is at times hard to locate. But with our toolsmiths ready for assistance at CVC, it took hardly a few clicks to reveal the magic behind the `vmm_atomic_gen(icu_xfer). Here is a first look at the atomic gen code inside DVE.

Once the desired text macro is selected, DVE has a “CSM – Context Sensitive Menu” to expand the macro with arguments. It is “Show à Macro”, as seen below in the screenshot.

With a quick bang go on DVE – the Macros expander popped up revealing the nicely expanded, with all class name argument substituted source code for the actual atomic_generator that gets created by the one liner macro. Along with clearly visible were the facade class name and the actual callback task with clear argument list (something that’s not obvious by looking at standard vmm.sv).

Now, what’s more – in DVE, you can bind such “nice feature” to a convenient hot-key if you like (say if you intend to use this feature often). Here is the trick:

Add the following to your $HOME/.synopsys_dve_usersetup.tcl

gui_set_hotkey -menu "Scope->Show->Macro" -hot_key "F6"

Now when you select a macro and type “F6” – the macro expands, no rocket science, but a cool convenient feature indeed!

The DVE’s macro expansion feature that makes debugging a real fun!

Renewed interest/investment in code linting! Good for the industry

As some of us have seen over last decade, approximately 5 years ago industry was upbeat about code/RTL linting with almost every EDA vendor offering products in this space. Some of them were start-ups acquired by big vendors (like LEDA.fr to Synopsys). At the end the Linting market proved too small for the 3 biggies and their focus on that technology got sidelined. In all, one company survived this wave well and that’s Atrenta – its SpyGlass product increased leaps and bounds both in its capabilities and installed base. Today SpyGlass is an undisputed leader in Linting and has enjoyed monopoly for more than 5 years, well done Atrenta!

Come recession, silently few smaller EDA vendors started investing on this niche segment and now we have ALINT from Aldec and Ascent from RealIntent. I’m personally thrilled to see more players on this technology – though the $$ may not be too high, the potential user base is large and investment is not all that HIGH as in a SystemVerilog simulator for instance.

From a user view though, Linting is a must have step in flow as recognized by experts like Adam Kronlik in a book: Functional Verification of Electronic Systems, Chapter 8 HDL Lint: http://www.iec.org/pubs/pub.asp?pid=13&bsi=3&cat=cont 

(BTW, I have a chapter on the same book, Chapter 14).

Few notes on 2 modern linters here:

Ascent from RealIntent: (http://www.realintent.com/real-intent-products/ascent).

One of the traditional challenges of a Linter has been the “heavy noise” it creates. Recent Linters *claim* to do better there – especially Ascent.

Other interesting features in this linter are:

• Opportunities to improve simulation performance
• Operations with hidden or expensive implementation costs

True, your mileage may vary, but good thoughts indeed!

As we read more on the Datasheet of Ascent one gets a feeling that it combines a traditional Modelchecker inside it as well – as their PBV & ABV features talk about. I’m not sure if that’s a good thing from a pricing standpoint as the linters are usually far cheaper than model checkers. But a good try by RealIntent indeed!

 

ALINT from Aldec (www.aldec.com)

Fairly young in the market (~2 years??), it has solid STARC policy inside it. What really interests me in this is their full blown API for user defined checks – yes every other vendor claims/has it in some manner, but I have not seen this level of detailed support and even better – their flexibility and response time in enhancing the API as needed.

It will be interesting to see how they survive over say next 5 years! Maybe it signals some impact to the erstwhile King of Linting – SpyGlass!

SystemVerilog Interfaces – learn more about it for free! Register Now for this Webinar

CVC is pleased to announce online Webinar on "SystemVerilog Interfaces" along with Aldec as our partner. With ever growing interest in the true power of SystemVerilog here is your opportunity to get started with SystemVerilog in good style with no additional cost - it is a FREE Webinar and is scheduled in 3 different times to suit various timezones across the globe - ASIA, Europe & USA.Register online NOW to book your seat!

ASIA - India 9.30-10.30 AM,China: 12.00 to 13.00

Europe - 15.00 to 16.00 CET

USA - 9.00 - 10.00 AM, PST

Click here for an abstract of the Webinar. It will be presented by Srinivasan Venkataramanan from CVC and Jaroslaw K, from Aldec.