SystemVerilog covergroup – bins and the value set matching

During our last week Verification with SystemVerilog class (VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ), an interesting question popped up during functional coverage session. As user defined bins are created for vectors in SystemVerilog, what if the value set range is not divisible by the specified number of bins (say in a fixed number of bins case)? 

Consider:

[cpp]

bit [4:0] vec_5bits;

covergroup cg;

  cp1 : coverpoint vec_5bits {

    bins four_buckets [4] = {[0:$]};

    bins five_buckets [5] = {[0:$]};

  bins fifty_buckets [50] = {[0:$]};

}

endgroup : cg

[/cpp]

Let’s analyze the above:

four_buckets –> simple, each contains 8 values, uniform

five_buckets –> 5 buckets, first 4 will have 6 values each, 5th bucket will contain all the remaining 8 values:

              [0,1,2,3,4,5], [6,7,8,9,10,11], [12..17], [18..23], [24,25,26,27,28,29,30,31]

fifty_bukcets –> first 32 bins will have 1 value each, remaining 18 shall remain empty!!

Questa prints a nice warning about the last case as below:

VSIM 1> run 990
# ** Warning: (vsim-8546) The number of values specified '32' is less than the size '50' of fixed-size array bin 'fifty_buckets' in Coverpoint 'cp_1' of Covergroup instance '\/top/spram_fcov_1/my_cg_0 '. The '18' empty bins will not contribute towards coverage.