Wednesday, February 24, 2010

Debug SystemVerilog code the right way with Verdi

Srinivasan Venkataramanan, CVC Pvt. Ltd. www.cvcblr.com

Sreenath V, CVC Pvt. Ltd. www.cvcblr.com

One of the many challenges in taking over a block developed by others is the quick ability to grasp the big picture fast and then delve deep into some focus areas. Talking of SystemVerilog based Verification code base (say with a base class such as VMM) is even more challenging as many engineers still find it new. During recent reviews at customer sites we often find engineers asking questions like:

1. How do I quickly know the various transactors in my environment? Of-course one can go through UNIX find-grep route, but with modern verification base, there has to be a modern approach to this ever lasting challenge as well.

2. With several macros being used to reduce the verbosity in coding, the reading/deciphering the code by a novice engineers becomes more challenging. If tools don’t address this part, it is possible that the benefits of code shrink by these macros may get quickly lost with the time being spent by a new engineer trying to understand it in detail.

SpringSoft’s Verdi (tm) has solid support for SystemVerilog testbenches with a full fledged Testbench browser, macro expander etc. It also provides a nice transaction debug capabilities, more on that on a separate blog soon.

What is nice about Verdi is the ability to get a quick view of inheritance structure via its Testbench Browser. See below for an example (look at the Green eclipse area). It is very easy to note the transactors derived from a base class such as vmm_xactor.

verdi_sv_inherit

 

On the second challenge, Verdi makes it very convenient to expand/collapse a macro.

1. Select the macro usage on the source window.

2. Press “Control-m” – expand macro; See below for a screenshot, l

3. The source window now has an expand/collapse icon (+/- symbol) to the left of the macro line.  (Green eclipse below)

4. When you expand, the “behind the scene” code gets colored on w white background quickly making it distinguished from rest of the code. ((Green rectangle below).

 

verdi_sv_macro_expansion

We recently had a customer asking for all VMM component code expanded, and it was merely a 15 minute job with this tiny little feature to get that done!

Happy debugging!

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