What’s new in Verification 2012? Pre-DAC 2012 analysis of exciting EDA solutions

With DAC around the corner, it is time to update our readers on what’s new in Verification in 2012 from EDA perspective. Here is what our TeamCVC have found so far as interesting, will be glad to add more if you drop us a note via info@cvcblr.com or as comments here in this blog itself!

Here is an alphabetical order of various vendors & their solutions.

AgniSys – your neighborhood automation solution for registers & more

If your design is all about IPs and sub-systems with say,more than 50 registers – you would be using one of the several formats (standard/proprietary) to define, maintain and manage the ever changing fields/blocks etc. If you have to manually code these registers in SystemVerilog/VMM/OVM/UVM/eRM – you know how hard it is, how laborious it is and how many hours it consumes to keep them upto-date. This is precisely where AgniSys fits into your flow. Basically their IDesignSpec is a plug-in to Word/XL/FrameMaker etc. to create register specification in various formats of your choice. Here is what it can do (picture below):

If you thought it can only be for Verification team, be ready for more: it generates:

• RTL code (for Reg RD/WR)
• C-headers for SW team
• UVM/VMM/OVM code for Verif teams
• Assertions
• Functional coverage etc.

All this and more for almost free – Yes indeed! They now offer a free version of their popular IDS for even “commercial use” – see: http://www.agnisys.com/products/66-idsfree 

Aldec’s Riviera-Pro brings UVM, OVM & VMM to desktop & on Cloud!

If you thought all the buzz around SystemVerilog, VMM/OVM/UVM is all for ASIC folks on Linux alone, be ready for some pleasant surprise! Aldec with its much praised easy-to-use tools like Active-HDL, ALINT etc. has built Riviera-Pro to bring these technologies to your laptops/desktops under Windows (and Linux of-course). Their intuitive debug and code-entry features are now available for SystemVerilog/UVM too. Do visit them at their booth or register via:http://www.aldec.com/en/events/sessions/38 to learn more about their debug features such as Transaction Recording, message displays etc.

Also they recently introduced Aldec Cloud – perhaps a bold step towards UVM on cloud!

 

Checkout their free trial @ http://www.aldec.com/en/solutions/functional_verification/aldec_cloud

Axiom’s MPSim & DesignerUVM – the latest in UVM tools!

If you were following the availability of multi-threaded simulators in the market, it is quite possible that you had noticed the front runner in this space – the MPSim from Axiom.  MPSim was the very first one to address the multi-core simulations in EDA domain and since then have grown leaps and bounds to become a strong SystemVerilog simulator with all methodologies such as VMM/OVM and UVM. It also has low power features like UPF that makes it a very compelling product for ASIC houses with large simulation requirements. Axiom is known for performance, but not just that!. It is infact their added debug capability that makes them even more compelling alternative to other vendors. In this Video interview, Tarak from Axiom explains their new debug feature DesignerUVM. 

Quoting Tarak: “You can do lot of simulations, but ultimately the engineering productivity comes from the ability to debug designs”:

We couldn’t agree more! It is Debug that takes whole lot of time and it is quite unfortunate major EDA vendors have not focused their R&D energy on this as much as they perhaps should. Consider the following scenarios in UVM environments:

• A factory override didn’t occur/work as you expected it to
• get_config_string failed to fecth correct value
• In an array of virtual interfaces being hooked up to physical interfaces, something went wrong and you observe incorrect drives/samples
• Port-to-export connections seem wrong

Does your existing Debugger(s) assist you in finding this? (besides gvim/Emacs, find, grep etc.)? If not – it is time to wake up and yell for more from your vendor. Now they have a reason to listen to you – as otherwise YOU as a customer have an alternate – the Axiom DesignerUVM will do these for you!

Breker Systems – SoC level verification

Breker with its new TrekSoC is one of the hottest EDA solutions to watch for – given the huge increase in number of System-On-Chips (SoC) being designed/integrated. Ask yourself:

• How long can you continue with manually written C-tests?
• How long can you maintain 2 (or more) test-env
  • One for Transaction/UVM based and
  • Another for the actual processor RTL based, that require C-tests?
• What about multi-threaded tests? Can we even write them by hand and synchronize?
• Won’t it be nice to have a “single source” for both TXN tests & C-tests?
• Can we truly “reuse” knowledge from IP DITL (Day In The Life) to SoC?
• Can we quickly reproduce SoC level issues at IP level with know extra effort?

These are just some of the “tip-of-the-iceberg” problems of SoC level verification that Breker is attempting to solve for you! For sure you don’t want to miss this – if you are in SoC world (who isn’t BTW?)

Cadence’s AVIP – Accelerated VIP, next form of “Synthesizable VIP”?

For quite a while the industry has been talking about “Synthesizable VIPs” for the want of putting them into FPGAs/Emulators and get more cycles out of DV tasks. VMM started it with VMM-HAL, then came the flurry of Virtual prototypes/platforms that promise to allow smooth integration of various abstraction models in a simulation/emulation env. Cadence’s recent announcement on AVIP is worth noting in this space, see them at DAC for more.

Mentor’s UVM Express, UVMConnect & more..

Mentor recently announced their extended UVM initiatives via UVM Express & UVM Connect:

Their Verification Academy initiative continues to be very popular among users, even non-Mentor customers. Hats off to Dave Rich for keeping the quality of discussions/responses very neutral and technical!

 

NextOp – Assertion Synthesis/Mesh generation

Whether you are doing IP level verification, sub-system or SoC – assertions are your friends – to detect bugs close to the source, apply formal search, indicate coverage holes etc. One of the biggest challenges in adopting them however is – who will write them? This ONE BIG Question has kept the ABV adoption way too slow for too long a period in the industry. But no longer..hopefully if your company can invest in right technology. NextOp with its patented “Assertion Synthesis” can provide you high quality properties:

Yunshan, CEO of NextOp will be in John’s Troublemaker panel, so be there to hear him or ask him live at DAC.

SparkEDA – Ignite your Verification

A quiet storm in the making, SparKEDA spearheaded by Alex Gnusin is creating some very interesting solutions. Its Panda Formal verifier claims simplicity all along. What we really liked on their demo to TeamCVC was their “ASTRA Wave” – an assertion & document creator straight from waveforms, see below for a screenshot. If it works as handy as it promises/claims – this is worth an addition to every Desktop indeed!

 

Specman is alive & kicking in 2012!

In quite contrast to the very many who believed that Specman & the e-language is dead – it is alive and kicking even well into 2012! See various views at DeepChip pages if you wish. But the ground reality from India and Europe is that there are millions of lines of e-code and more is being written as we speak – some by our own TeamCVC for local customers here who simply refuse to move away from the all powerful IEEE 1647 e-language. The eWG http://standards.ieee.org/develop/wg/eWG.html has recently finished its latest LRM updates (read: http://www.cvcblr.com/blog/?p=333). Cadence continues its updates to Specman with features like:

• Parallel compile
• Compiled mode debug
• Save-restore, reseed on the fly etc.

The latest ClubT was held in Israel in Mar 2012 and hopefully sometime soon in India as well!

Synopsys DAC updates

Since the recent nSys acquisition, Synopsys’s VIP portfolio has become very strong and one can expect more native UVM VIPs from them soon. For DAC 2012 specifically their AMS story sounds interesting: http://bit.ly/KYVIBj

On “Verification Luncheon” they plan to talk about SoC level verification. Sure they would showcase the performance improvements to VCS, but hopefully they will also demo their approach to the manual C-test creation monster soon!

UVM 1.1b is almost there

Most of you are following the UVM development at Accellera and DAC is a great time to release a high quality version of ever growing UVM code base. Learn more about what’s new, and what’s lined up for UVM 1.2 etc. at: http://www.accellera.org/downloads/standards/uvm

What about UVM-like for VHDL users?

If you are a VHDL user and have been feeling let down by the marketing bigwigs of EDA vendors – don’t worry, here is OS-VVM for you: Originating from VHDL guru Jim Lewis through his several years of experience, OS-VMM provides:

• Constrained Random generation
• Coverage Model capturing

all in native VHDL. Add this to the most powerful temporal languages available for hardware design industry – the IEEE 1850 PSL – it is a great compelling solution for VHDL users indeed. BTW – if you didn’t know, VHDL 2008 version already incorporates PSL into it, so you just a VHDL license with your EDA tool to run ABV, CRV & CDV (unlike the relatively expensive SystemVerilog solutions), learn more at: http://www.cvcblr.com/blog/?p=436 

Other interesting ones:

Here are some of the other ones you might be interested in:

• EVE – its ZeBu is making more news
• Blue Pearl  -relatively new entrant made some noise about generating SDC/Constraints etc.
• Xilinx’s new Vivado is in the news for its latest SystemVerilog additions and all new ISIM simulator. It is yet to be seen how much UVM support they will add in ISM in years to come.
• RealIntent’s X-finder is another niche point tool that some of you may like!
• UVM Linter from AMIQ

 

Technorati Tags: EDA,Specman,SystemVerilog,DAC

A fairy tale on SystemVerilog MDAs and UVM field macros

 

In one of the semiconductor conferences, Dr. Satya Gupta http://bit.ly/KlQpxr mentioned on a lighter note that the Semiconductor/VLSI needs to be promoted more among young Indian engineers and need to be made more “attractive”. (Guess it was Mentor’s U-2-U in 2010, anyone?) – few of the panelists and audience threw out ideas on how to do the same – via contests, TV shows etc. Taking it little more seriously and using social media we at CVC (www.cvcblr.com) believe our blogs/tweets & Facebook updates are doing exactly that.

Here is a “fairy tale” on how SystemVerilog MDAs work (or not work) with UVM field macros. Consider that we have a 3-D array (2 unpacked dimensions and 1 packed dimension) as shown below (“mda_3d” in s2p_xactn below):

While it sounds simple enough, the devil lies in “detail”. When you need to copy/clone/compare you need to ensure this mda_3d is included just like other fields. Huh? That’s what UVM supports via “field_macros” isn’t it? How about:

 

Oh my dear! Hold your breadth – this works for scalar types, and for 1-D arrays but NOT beyond :-( . Since System Verilog supports “arbitrary” dimensions in MDAs (Multi-Dimensional Arrays), the UVM base class doesn’t provide macros beyond 1-D arrays. Bummer, so what’s next? Here is your helpline – the uvm_object::do_copy.

Here is a simple code snippet that augments the built-in automated “copy” routine to include user defined MDA such as our “mda_3d”.

 

 

With that – UVM has once again proven that while it is not obvious why it has so many hidden “gems” – they are all useful on a case-to-case basis. In Hindi we say “Har eak cheez zaroori hota hai”. As the popular AirTel advertisement goes (India specific, for International readers, see: AirTel commercial ad). In case you can related your facebook friends to UVM “features/functions/base classes” and wonder “How come I have so many friends” – as the ad says “Every friend is useful”

 

 

Happy UVM-ing.

TeamCVC

Technorati Tags: SystemVerilog,UVM

CRV, CDV & ABV for VHDL users – all native

If you have been in the ASIC/FPGA industry for the past 5 years or so, it is highly unlikely that you haven’t heard of these buzz words:

• ABV – Assertion Based Verification
• CRV – Constrained Random Verification
• CDV – Coverage Driven Verification

While many ASIC teams have started using these in mainstream, FPGA users are still catching up with theses. One of the primary reasons has been that many FPGA designers use VHDL for RTL and Testench traditionally. (Though there are some high end Verilog users too, let’s talk about them in a separate blog. Meanwhile those folks can see how to adopt System Verilog for FPGAs from: http://slidesha.re/KtLlFu )

While these modern verification technologies are language independent, there is an impression in the industry that they are provided only via SystemVerilog and is thus restricted for Verilog/SV users. Some VHDL RTL teams have been forced to migrate to SystemVerilog just for this purpose – frankly speaking, a die-hard VHDL fan wouldn’t like it and also for teams using VHDL for long it is way too hard to do this migration in short timeframe. More important question is – do I need to migrate to adopt these technologies? – The answer is technically NO. VHDL has been very strong in “adaptability” to various requirements and stood strong amidst tough competition. Its rich features such as overloading, encapsulation (via packages), configurations, data structures etc. have been exploited by various applications such as: modeling, RTL design, testbenches etc.

Assertion Based Verification in VHDL

 

Recently temporal assertions capability has been added to native VHDL from IEEE 1850-PSL and hence the new VHDL 2009 standard has full fledged temporal expressiveness natively. See a PSL tutorial @ http://www.project-veripage.com/psl_tutorial_1.php

Constrained Random Verification

Given the complexity of designs being done using VHDL and FPGAs it is becoming increasingly difficult to rely just on directed stimulus. Constrained random generation allows exploring newer paths in every simulation run.

VHDL with its package capability allows building constrained random generation feature natively into the language without much hassle. Recently released OS-VMM infact provides it off-the-shelf. See: http://osvvm.org/archives/category/randomization

Coverage Driven Verification

Coverage as a metric to measure verification progress has been around for decades in verification. Code coverage has been widely used by RTL teams. Recently Assertions via PSL-VHDL provide temporal coverage and can be very handy to capture functional coverage of control oriented features. For data oriented features, coverpoint, cross etc. can be created in VHDL via packages. And OS-VMM does exactly that for all VHDL users. See: http://osvvm.org/archives/339

 

In summary – all the modern verification technologies are now available to VHDL users natively – without any additional cost (of a mixed language simulator for instance). The OS-VVM is a great starting point for coverage & constraints and PSL-VHDL provides all the temporal capabilities. Start doing better verification in VHDL with: http://www.osvvm.org

What is “special” about SystemVerilog’s new - constructor

During one of our recent VSV training sessions, a smart attendee asked few interesting questions about SystemVerilog’s new constructor. Questions like:

1. Is it similar to other functions in Verilog/SV?

2. Is it virtual?

3. What is the return type of the same?

4. How does inheritance work for new ?

So here is a blog entry that delves into the “details”.

First of all – it is a function – so it can only have non-time consuming stuff (BTW, a task can be invoked via fork..join_none from within a function).

It is NOT a virtual function. It is illegal to declare it “virtual”.

On the return “type” – it is different from other functions – it is very “adaptive in nature” – i.e. it returns what the LHS requires. i.e. it returns an object of the type of the handle that appears on the LHS. Hence there is NO return type declared for this special function.

Things get very interesting/special when a new class is derived from a base class. With any other System Verilog function/task, you have 3 options while doing inheritance:

1. Override base class behavior
2. Add//append to base class behavior
3. Prepend to base class behavior

For those who are familiar with E, IEEE 1647 language, it is equivalent to

1. is only (override)
2. is also (append)
3. is first (prepend)

However when it comes to this special new function – it always an “append behavior” (“is also” – as in E/Specman): Let’s look at some code & results;

Consider the code below:

Since only a derived object is constructed and there is no call to super.new explicitly one might expect only the message from derived class’s new.

But see what Questa (www.mentor.com/questa) does:

So that’s one “special” behavior of new. i.e. whether or not you call the base class’s constructor – it always gets called implicitly.

To prove this point and to see if we can play some “tricks” with it, here is a small variant code below;

In the above code we just added an argument called “id” to the base class constructor. In the derived we decided to “forget” about it. If it was a “virtual” function, as per the semantics, this would be illegal – i.e. the function prototype/signature must remain same across inheritance. However the re-definition of new in derived class is just fine. However, there is still an error: recall that the base’s new is always called – now the “id” argument is NOT provided for the implicit call to new. So what does our friendly compiler Questa say for this? See below;

 

 

So the error message is clear enough as to how it can be fixed. Below is a possible fix:

 

Now, as a last experiment for this blog, why do we claim only is also is allowed for new ? What if I try other way? See the result below:

 

Here is what LRM IEEE 1800-2009 has to say for this:

When using the super within new, super.new shall be the first statement executed in the constructor. This
is because the superclass shall be initialized before the current class and, if the user code does not provide an
initialization, the compiler shall insert a call to super.new automatically.

 

So hopefully you are convinced that the simple looking function new  is indeed “special” function in SystemVerilog.

Happy new-ing :-)

TeamCVC

www.cvcblr.com/blog

New to System Verilog - UVM? Wonder why it exits at time zero?

With UVM http://www.uvmworld.org/ adding a good framework around SystemVerilog, several ASIC design teams have taken the first step in adopting it in full form. Many are migrating from either OVM or VMM and many others are plain SystemVerilog and/or Verilog users.

 

One of the significant changes in latest UVM (1.1 onwards) is the so called “phasing” – it is a feature motivated from VMM users and more HW related requirement overlaid on top of more SW centric OVM-like phasing. Refer to a detailed paper on this topic from Intel + CVC @ SNUG India 2011 via: http://bit.ly/JL9x30 

A direct impact of this new phasing in UVM 1.1 is that a smooth running test in OVM/plain SystemVerilog is likely terminate “prematurely” in UVM. This is typical when a first time user adds a UVM test as below:

 

While everything seems normal as in OVM, here is a sample run.log from this test:

 

 

The new phasing seems to be in effect :

• – the reset_phase is kicking and takes its sweet 100 ns of simulation time.
• Sequence starts off
• But hold on.. why on earth is it exiting? Aren’t you supposed to run/execute that sequence for me?

The crux of this has to with the so called run time semantics of “task based phases” in UVM base class library. For those interested, here is a snippet of that documentation:

// Task: main_phase
//
// The <main_phase> phase implementation method.
//
// This task returning or not does not indicate the end
// or persistence of this phase.

And at implementation level, here is what a relevant piece of UVM base class code that does it for you:

 

Now you say Aha! That explains why my test::main_phase didn’t wait for “seq.start” to finish.

Now you may ask why and more interestingly is it a BUG in UVM? Not really, this is intended, read more of UVM code/doc:

 

//

// Task: main_phase
//
// The <main_phase> phase implementation method.
//
// This task returning or not does not indicate the end
// or persistence of this phase.

It is necessary to raise an objection
// using ~phase.raise_objection()~ to cause the phase to persist.
// Once all components have dropped their respective objection
// using ~phase.drop_objection()~, or if no components raises an
// objection, the phase is ended.
//

Now that you understand why it happens, here is the fix for it:

 

Happy UVM-ing. Do call us for quick ramp-up of yourself/your team, we have some great training sessions on the same at: http://www.cvcblr.com/trainings 

TeamCVC

www.cvcblr.com/blog

Do you care for better error messaging in SystemVerilog compiler?

With so much fever around SystemVerilog in the verification community, more and more junior engineers are picking up System Verilog. Infact several universities started teaching System Verilog as part of advanced VLSI degree. And with its availability in Desktop based simulators like FPGA design tool chain, more and more FPGA designers are looking at it, and adopting it rapidly.

Clearly SystemVerilog with its all gun blazing features are useful for FPGA community at large, our CTO Srini presented this at FPGA Camp in Bangalore few years ago: http://www.slideshare.net/mobile/fpgacentral/upgrading-to-system-verilog-for-fpga-designs-srinivasan-venkataramanan-cvc 

Since then we have trained several FPGA teams on using:

• SystemVerilog for Design (SVD: http://www.cvcblr.com/trng_profiles/CVC_LG_SVD_profile.pdf)
• SystemVerilog Assertions: (SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf)
• VSV: (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf)

One of the things we have learnt throughout this journey with FPGA folks is that they care a lot for usability of EDA tools and they are much more demanding than their ASIC Design counterparts on features like:

• IDE – Integrated Design/Development Environment
• Clear cut error messages from the compiler/tool
• Pin point the source file-line easily

While SystemVerilog in its early years was used primarily by ASIC teams the above features were not that critical. But now with 5 EDA vendors supporting SystemVerilog + UVM + SVA, customers are at good position to demand what they need! BTW –who are the 5 EDA vendors?

• Synopsys (www.synopsys.com)
• Mentor (www.mentor.com)
• Cadence (www.cadence.com)
• Aldec (www.aldec.com)
• Axiom (www.axiom-da.com)

And CVC (www.cvcblr.com) is partner with all of them and is uniquely positioned in the world to provide EDA vendor neutral training sessions. Infact recently we have enabled majority of our training labs (See the full list at: http://www.cvcblr.com/trainings)  to run on all these 5 tools.

Coming back to the use model requirements, here is a screenshot of how Riviera-Pro from Aldec points a common code error in SystemVerilog. Consider the following piece of code: Can you spot what’s wrong?

 

 

Of-course with the “dotted” eclipse, most of you should (if not, we strongly suggest you attend our VSV course ASAP: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf)

here is a screenshot of how Riviera-Pro from Aldec (www.aldec.com) points a common code error in SystemVerilog.

 

So – hold no more, even if you are a plain Desktop user with limited budget, SystemVerilog is at your reach!

TeamCVC

www.cvcblr.com/blog

Real number randomization in SystemVerilog

 

Folks working on AMS (Analog & Mixed Signal) Design-Verification often require real numbers for things like Signal-to-Noise-Ratio (SNR). With so much buzz around SystemVerilog and its clear strengths on Constrained Random Verification support, engineers wonder how they could leverage it for “real randomization”.

Unfortunately SystemVerilog doesn’t directly support “rand real” declaration (weird reasons given by EDA developers, while a google on “random float number” reveals quite a few hits). However recall that SystemVerilog is built on top of Verilog and Verilog has some beautiful twin-functions for real <—> bits:

 

$bitstoreal

$realtobits

Here is a neat trick to use them for a signal-to-noise ratio random generation (Problem originally reported at: http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=4413)

 

Notes:

1. We have used new SystemVerilog 2009 syntax for “extern” constraint – nice one indeed to be in line with extern tasks/functions.

2. Also the %p –> Very handy one indeed

3. Used the post_randomize() for one of its best use models – display what got generated automatically. We teach this in our VSV training (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) and every customer appreciates that use-case for post_randomize.

 

 

In case you want to learn SystemVerilog and jump onto this bandwagon before it is too late, join our training seesions – weekdays, part-time or weekend, see: http://www.cvcblr.com/trainings for details.

 

Enjoy SystemVerilog & AMS

TeamCVC

www.cvcblr.com/blog