SystemVerilog tip: watch out enum and randc

Recently an interesting question was raised by SystemVerilog user on randc usage with enum. To illustrate, consider the following code:

[cpp]
typedef enum {red, green, blue, yellow, white} house_color_type;
class c;
randc house_color_type enum_0;
[/cpp]

Spot anything wrong above? Perhaps not? As it goes with randc an implementation needs to remember all values generated so far before recycling! So it does consume extra memory. SV LRM says:

To reduce memory requirements, implementations may impose a limit on the maximum size of a randc
variable, but it shall be no less than 8 bits.

By default an enum is an int – i.e. 32-bits, hence allowing a randc on it blindly is a real challenge for tools – though some advanced tools/versions (Questa 6.5a for instance) allows it. But this default int choice is not something I like so much – it should have been cleverer to choose appropriate sized of vector by the implementation, did we not know LRM committee is often biased by implementers. No pun intended, but just MHO.

Anyway coming back to the question, a very useful tip here (like “Moral of the story is..” – something that’s day-to-day phrase in a typical school boy father’s life , something that I thoroughly enjoy, thanks to my Anirudh Pradyumnan): Model your enum size while declaring it. As in:

[cpp]

typedef enum {red, green, blue, yellow, white} house_color_type;

typedef enum bit [2:0] {red, green, blue, yellow, white} house_color_type_BETTER;

[/cpp]