SystemVerilog for Verification: Easier PLI integration with MPSim

Several engineers working and aspiring to work in the field of ASIC front-end design/verification tend to stay away from Verilog’s powerful PLI/VPI – some of them because they see it as old technology and many others – simply “FEAR” from it, thanks to its complex integration with the tools.

For those who believe it is old technology – think again, most of the cutting edge EDA innovations (in front end) happening around verification use Verilog’s PLI/VPI to talk to your underlying simulator. To quote a few examples:

NextOp/Atrenta’s BugScope
Novas’s Verdi/Debussy
Axiom’s @Designer http://www.axiom-da.com (Debugger that can work with all standard Verilog simulators)
Trek from Brekersystems (www.brekersystems.com)
OnPoint from vennsa-da.com

Now for those who “fear” from VPI due to its integration challenges – to be fair – you’ve reasons to do so. However advanced functional verification solutions such as VCS, MPSim (http://www.axiom-da.com ) provide a convenient TABLE format to ease this task. All you need to do is to create the following table:

And use standard gcc to compile your C-code as below:

gcc -m32 -pipe -c -g ../pr_tscale.c -I$(ATHDLROOT)/tb/incl –DAXIOM

Now, invoke the atsim compiler with the tab-file as shown in below command:

atsim -c ../pr_tscale.v +tabfile+pr_tscale.tab +pliobj+../pr_tscale.o
./athdl_sv

For those trying it out at your end, notice the path to the *.o file should have “../” as the atsim compiled one-dir below (hidden dir).

Now if it was this simple, why would anyone FEAR from it really? The answer is – that’s how the Verilog LRM defines it to be, see below if you have time and patience. Advanced verification platforms like MPSim will hide these details for you for your pleasure adn ease-of-use!

For those uninitiated with this fear, see how the Verilog LRM defines a data structure for this purpose below: (extract from standard vpi_user.h)

Now to use it in an end-user application such as the one found at: http://www.cvcblr.com/blog/?p=517 one needs to create a variable of this structure and fill in the integration details, see below: