As we wrap up an excellent UVM training for a well informed audience for a local customer at the very beginning of 2013, here is a quick tip for those verification work-horses trying to debug various UVM phase related hangs in their simulations. To be honest, this was developed for another customer way back in the middle of 2012, but never got published, so we decided to do it in early 2013. This is part of our 
The scenario that several customers face is that they have bunch of raise & drop objections, but somehow there is a mismatch of the “raise-to-drop” – i.e. some of the raised objections remained and never got dropped! While UVM comes with few handy plusargs - +UVM_PHASE_TRACE, +UVM_OBJECTION_TRACE etc. these don’t always point you to exact problem, atleast fast-enough. Here is a smarter approach:
The uvm_objection base class provides a very nice debug routine named display_objections(). One may want to stick the following piece of debug code to a test:
Fork the above task along with your regular main_phase’s logic. When we run this in Questa for instance, here is what we get:
So the above indicates there are 3 folks opposing it with clear pointers to who they are. Now run further till you get the hang state, you should see:
The above transcript clearly indicates that the monitor is the culprit that has a raise objection that’s not dropped yet!
Good Luck and have fun with your SystemVerilog and UVM debug. Contact us via http://www.cvcblr.com/about_us if your team need hands-on problem solving level case studies such as above along with regular VSV, UVM training (http://www.cvcblr.com/trainings).
No comments:
Post a Comment