Mind the GAP – even in SystemVerilog macro definition

SystemVerilog enhances the TEXT-MACRO feature (a.k.a `define-s by many young engineers) of Verilog by a good length. Significant enhancements done are:

1. Added capability to extend the definition to multiple lines
2. Added macros with arguments;
3. Macro arguments can have default values too! (not fully supported by all tools though)

However there are few caveats – in general any text-macro usage in any computer language is hard to debug when it fails to compile. So be ready to be patient while debugging macro code.

Recently an online forum user asked a question on SystemVerilog macros. Here is what the user defined to start with:

To a bare eye, the above looks fine. However a  SV compiler would through an error at it. As per the LRM:

 

If formal arguments are used, the list of formal argument names shall be enclosed in parentheses following
the name of the macro. The left parenthesis shall follow the text macro name immediately, with no space in
between.

In other words – as it is with any Metro station sign, you should be careful with the GAP/spaces :-)

Notice that “extra space” after the macro name CHECK1 is now gone! This works in Questa 10.2.

So next time when you code your macros – mind the GAP :-)

TeamCVC

Technorati Tags: SystemVerilog,Verilog,EDA

Smart constraint modeling in SystemVerilog

With SystemVerilog language gaining popularity among user, it is getting interesting to see user asking similar/repeating “patterns” of challenges in various forums. One of them is on constraint modeling when it becomes more than simple “a > 10” like stuff. Recently a VerifAcademy user asked:

 

in my testbench i have to make a random signal "[31:0] distortion". it must contain one (or, in other case, two) hot bit(s) (hot bit is "1", all others are "0"). So i have a problem with writing a constraint: i really don't want to write all possible combinations of these bits (if there are two of them, there will be 32! combinations, so...). Does anyone have solution for this problem?

 

A smart model is indeed available via 2 features of this vast language – System Verilog:

1. A handy system function to count the number of “ones”

2. Constraints can use functions in expressions.

Combining the above two, here is a full solution to the above problem along with a sample run from Questa 10.2

 

Hope you enjoy the concise solution. Do call us via +91-9620209226 or training@cvcblr.com for learning more about this wonderful language and its applicability for your verification projects.

TeamCVC

 

 

Technorati Tags: systemVerilog,EDA

SV solver puzzle part II – “guidance” vs. “dictation”

 

With one of our recent blog entries on SystemVerilog constraint solver (http://www.cvcblr.com/blog/?p=725) becoming so popular, several readers have contacted us via email to know little more about the puzzle. Specifically they wanted to understand how the solver ordering of variables is determined. Consider the same example as in that previous blog entry:

As noted in the previous blog, this creates an “implicit ordering” of variables – i.e. ‘v1” is solved BEFORE “v2”. A smart engineer (Muthurasu Sivaramakrishnan) asked this:

• Nice one. However, why cant we use Solve.. Before constraint in this scenario?

The answer is a little involved with yet-another subtlety in the language, and hence this new entry:

This reader’s question boils down to whether the above constraint “cst_ordered” is same as the following;

constraint cst_guidance {solve v1 before v2;}

First intuition says YES, but the answer unfortunately is NO. In SV there are 2 kinds of solver ordering - an ordering constraint is more of a "guidance on probability" and does NOT change the solution space. Hence it can't lead to a failure from a success or vice-versa. This is what happens with a solve..before – i.e. it is simply a “guidance” or suggestion to the solver.

However the ordering that gets enforced via function call is more STRICT/DICTATIVE in nature. It enforces the order by further "subdividing" the solution space and in a sense invokes the solver twice. In Questa you can actually see this in action via -solveverbose - you will see 2 "Working Set" prints for function based constraint:

1. First the solver gets “dictated” to solve “v1” INDEPENDENTLY. In a random choice, say it picked a value “1”

2. Now the solver takes up the next variable to be solved in THAT order, i.e. “v2” – you see in Questa the “Working Set’ print with details (note: randomize is called only once per iteration in user code)

 

So this leads to a constraint solver failure. Whereas a mere “guidance” shown by a solve..before would have solved both the variables TOGETHER, leading to a successful solving operation.

Bottomline: The function call “strictly enforces” the solve order, while the “solve..before” is more of a “guidance/suggestion”.

To learn more about this and other advanced SystemVerilog topics, join our training via www.cvcblr.com/trainings

Good Luck

TeamCVC 

Technorati Tags: SystemVerilog,EDA,Constraints,Questa

SVA: default disable – a boon or a bane?

As the SVA usage expands/grows in the industry, so do the language syntax/features. One of the recent (2009) addition to System Verilog language was the ability to code “default disabling condition”.

It is very handy to have an “inferred” disabling condition for all assertions so that one can save on verbosity while typing – every assertion doesn’t have to repeat;

  a_without_default_disable : assert property (disable iff (!rst_n) my_prop);

vs.

a_with_default_disable : assert property (my_prop);

Obviously anything that helps to save some typing is a BOON.

However there are some special category of assertions that may get unintentionally disabled by this. For instance the “reset-checks” – assertions that check the reset value of various DUT outputs. For e.g.

• FIFO empty flag during reset
• serialout signal from a de-serializer design

We recently had a similar DUT being verified with SVA. In the below code, notice the “default disable” and the reset-check

As the callout/marking shows – there is a bug in DUT, the signal “serialout” is indeed HIGH during reset, yet the assertion doesn’t fire (Questa shows it as INACTIVE – meaning it is a vacuous success in this case).

So that begs the question of “is the default disable a boon or a BANE”?       

The answer is – you need a methodology and a plan while doing your assertions – categorize the assertions appropriately. Specifically group them as:

• Reset checks
• Functional checks
• Low Power checks

etc. Here is a nice work-around for this:

• Use an explicit “disable iff (1’b0)” for those special category assertions

 

Now Questa flags it nicely as below:

So do use the new SVA stuff on “default disable” – it is indeed a BOON. Just make sure you “think” before you code those special category of assertions.

This is part of our larger story of ABV methodology being rolled out as next generation verification training sessions at CVC. So do contact us via training@cvcblr.com  for more advanced, practical usage of this wonderful technology.

Good Luck

TeamCVC

Technorati Tags: SystemVerilog,SVA,ABV

SystemVerilog constraint puzzle – treat for CRV lovers

Are you an avid fan of CRV – Constraint Random Verification? Have you played enough with System Verilog constraints? Many of our customers having attended our regular VSV training (http://www.cvcblr.com/trainings) do become so! One of the nice features of SystemVerilog constraint mechanism is its “bi-directionality” – a key feature that makes the distribution fairly wide spread and makes the state space well covered.

The industry has learnt it over the last decade of CRV usage – bidirectional constraints are better than unidirectional ones (that was the default in previous generation solver inside popular tool like Specman – called PGen. Even Specman has moved to a more robust, bi-directional IGEN/Intelligen few years back).

In SV this bi-directionality is subtle. Consider the code below:

To an average SV engineer the above 2 constraints look “same” as the function is trivially doing a return job. However they are different for an avid SV user or a solid SV solver such as Questa from Mentor. As per LRM:

Random variables used as function arguments shall establish an implicit variable ordering.

Hence in case of “cst_ordered”, the variable “v1” is solved FIRST and then the “v2” – i.e. they are solved separately and not together (Which is what happens with ‘cst_bidir”).

So what’s the big deal? Consider “v1” is chosen to be “1” first, then the solver has NO solution for “v2” :-( leading to a constraint failure.

So, next time when you use a function in a constraint, remember/recall/read this blog :-)

Care for a proof? See what Questa’s solveverbose prints:

qverilog file.sv –R –solveverbose=2

Enjoy CRV, enjoy SystemVerilog. In case you want to delve deeper into SV, do call us via training@cvcblr.com

TeamCVC

Technorati Tags: SystemVerilog,EDA,Questa

Is your UVM simulation hanging? Need a debug help? Use display_objections()

  As we wrap up an excellent UVM training for a well informed audience for a local customer at the very beginning of 2013, here is a quick tip for those verification work-horses trying to debug various UVM phase related hangs in their simulations. To be honest, this was developed for another customer way back in the middle of 2012, but never got published, so we decided to do it in early 2013. This is part of our product line where-in we line up various solutions around UVM.

The scenario that several customers face is that they have bunch of raise & drop objections, but somehow there is a mismatch of the “raise-to-drop” – i.e. some of the raised objections remained and never got dropped! While UVM comes with few handy plusargs - +UVM_PHASE_TRACE, +UVM_OBJECTION_TRACE etc. these don’t always point you to exact problem, atleast fast-enough. Here is a smarter approach:

The uvm_objection base class provides a very nice debug routine named display_objections(). One may want to stick the following piece of debug code to a test:

 

Fork the above task along with your regular main_phase’s logic. When we run this in Questa for instance, here is what we get:

 

So the above indicates there are 3 folks opposing it with clear pointers to who they are. Now run further till you get the hang state, you should see:

 

The above transcript clearly indicates that the monitor is the culprit that has a raise objection that’s not dropped yet!

Good Luck and have fun with your SystemVerilog and UVM debug. Contact us via http://www.cvcblr.com/about_us if your team need hands-on problem solving level case studies such as above along with regular VSV, UVM training (http://www.cvcblr.com/trainings).

TeamCVC

www.cvcblr.com/blog

Technorati Tags: SystemVerilog,UVM,EDA,training

I know SystemVerilog, why bother me with UVM?

If you are a verification engineer in ASIC/FPGA domain, chances are very little that you have not heard of SystemVerilog. For the last 6+ years it has been making positive impacts to design and verification teams across digital design space.

Given this fact, this is no surprise there are several young engineers who jumped on to the bandwagon and picked up the language to a certain level. Many successful engineers in this part of the world have taken CVC’s VSV course as a wise step towards the same.

However when it comes to the production use, plain System Verilog falls behind in certain key areas. Make no mistake, it is a powerful language and is becoming even more powerful with the upcoming 2012 update. See our blog for more on those updates: www.cvcblr.com/blog

Many users ask us – why do I need UVM on top of SystemVerilog. While there are ample number of marketing material available on the net for free on this, here is a humble, technical attempt to challenge a solid DV engineer with decent SV skills.

Consider a simple Deserializer design: call it S2P (Serial-2-Parallel converter). It captures the input serial stream from start-to-end and sends out as parallel data at its output every 8 clocks. A typical waveform would look as below:

Now, let’s say that you are SV aware to the extent that you can comfortably create a verification environment in say 1 or 2 hours for this simple design.

Now let’s try and do “verification” – add a negative test – i.e. create a scenario in which:

• There are ser_sop with NO ser_eop in between

See a sample screenshot below:

Remember, it is a negative test and hence you are NOT allowed to change any existing code. Can you achieve this in plain SystemVerilog without UVM?

If the answer is simple YES, we would love to hear your solution (add via comments here, below). No, don’t think of tricks like “force/release” etc. Attempt it as a pure SystemVerilog coding exercise.

The reality is – of-course we can, if we architect it upfront with factory and/or callback. That’s kind of what a framework such as UVM does for you. So UVM is nothing but 100% SystemVerilog, but wrapped in with a series of base-classes, built-in features that make your ‘verification” easy.

Join us for our upcoming UVM training session to know more on this challenge.

Bottomline – UVM is made to make your verification task easier, though it achieves it through a myriad of base classes. Luckily, users need to bother with only about half-a-dozen of them or maybe 10. But that’s only if you are educated well on UVM and trained by experts. If not, chances are you will loose yourself in the UVM base-class maze trying to make a decent way-out! Choice is yours!

Technorati Tags: SystemVerilog,EDA,UVM

Did you miss multiple-inheritance in SystemVerilog?

As some of our customers ask during our advanced SystemVerilog/UVM training sessions, SystemVerilog doesn’t allow multiple-inheritance. Or to be precise “DID NOT have”, now in SV-2012/2013 it does!

For those yet to get there – here is  a quick recap:

    Simple inheritance                  Few derived classes

        

 

One can of-course “derive” from another “derived class” too, as-in:

 

This is used widely in good System Verilog code and in general any OOP code. UVM uses this a lot as many of you who have been fortunate to have attended our popular UVM training sessions (http://www.cvcblr.com/trainings) across the world (Yes, we have delivered across India, various cities, across the globe as in Europe, Asia etc.).

However what was not allowed in older SystemVerilog (2005/2009) is:

Multiple inheritance, as in:

                                              

 

Now one may argue this is not all the time needed etc. If you need to get that interesting debate, a good starting point for you could be: http://en.wikipedia.org/wiki/Multiple_inheritance 

Come to think of it, UVM supports TLM ports and that requires multiple inheritance at the core: See the UML diagram for today’s UVM TLM:

 

 

i.e. the class uvm_port_base extends (and implements) a standard TLM-INTERFACE class (call it uvm_tlm_if_base). It is also “hierarchical” and can do better with certain characteristics of a uvm_component such as “instance path”, “parent” etc. The current UVM implementation “works-around” the limitation of SV 2005/2009 by instantiating a local uvm_component instance as a member and provides “proxy” methods to mimic the effect of multiple inheritance.

So below is a sample code using Multiple inheritance feature that is now added to P1800-2012 SystemVerilog standard. It does so by introducing few new keywords/constructs:

• interface class
• class implements

In near future your UVM base class could be remodeled as below (not full code obviously):

              

And voila, the uvm_tlm_port_base implements if_base, port_comp…

 

As we end 2012, start pushing your friendly EDA vendor for this new stuff as early as Q1-2013! Yes, we have this running at CVC with a popular, leading edge tool!

Happy New Year 2013 to all our readers. Equip yourself with all updates on SystemVerilog by signing up for our upcoming sessions at CVC, contact training@cvcblr.com for more!

 

Technorati Tags: SystemVerilog,EDA,inheitance,OOP,multiple inheritance

SV-DPI debug champion – your handy –dpiheader option

Ever played with SystemVerilog DPI (Direct Programming Interface)? Most of the verification engineers coming from EC/EE background, they have hard time debugging C code in general.

Things get complicated when you deal with multi-logic-valued system such as Verilog/SV (0,1,Z,X) and 2-state system such as C. See the standard data type matching slide we deliver during our popular VSV training: (http://www.cvcblr.com/trainings):

 

In case you can memorize the table above and use it each and every time when you touch DPI – perhaps you maynot need this post much. But for the 99.9% users who don’t or don’t want to do that, tools like Questa provide you a very handy option called -dpiheader Let’s see it in action: Consider a simple DPI import declaration as below:

 

Corresponding C-code looks like:

So far so good? For those who have “spotted” the bug, pat yourself and continue reading. Others – any issue so far? Let’s see what the simulation output from Questa looks like:

Now all your debug skills ON..go, chase and find that little:

If you go back to the basics – default argument data type for SV task is logic and is single bit in size. On SV side we had

output data)

On C/DPI side the corresponding mapping as per LRM is:

Whereas what we intended was to use a plain “int” for “data” – the example is kind of trivial to keep things simple and in perspective. Realize that in reality this can be fairly cumbersome mapping to memorize and/or remember.

Here is where the “debug champion” helps – your friendly –depheader option to vlog command.

When you run this, you get an output header file “sv_auto_hdrs_for_c.h”. It is best to include this to your C-code:

 

Now during “vsim” step, the Questa invokes C-compiler and it detects the type-mismatch in arguments on SV vs. C-side. On SV side we said “output data” – indicating it is a 4-state, 1-bit variable, while on C-side we declared it as “int”:

 

 

Now that’s by far a much better issue to debug than the simulation/runtime mismatch of values in C and SV side.

So next time you attempt to use SystemVerilog DPI make sure you read this blog and use the –dpiheader option with Questa. And if your team needs experts, hands-on training on SystemVerilog, contact us via: www.cvcblr.com/about_us

Technorati Tags: SystemVerilog,EDA,DPI,debug

Bringing in uniqueness constraint to SystemVerilog – welcome P1800-2012

If you are involved in functional verification I am sure you have atleast heard of System Verilog as the IEEE standard. The first IEEE standard was released back in 2005 and went in for a revision during 2009. Now there is yet another major update – 2012, expected to be fully ratified by early 2013 (on time for DVCon 2013). Here is a nice blog on this: http://blogs.mentor.com/verificationhorizons/blog/tag/ben-cohen/

A major part of this new version is all about assertions/SVA. If you need a detailed list of changes and examples, with applications – look no further, get hold of our new SVA 3rd edition @ SVA book 3rd edition @Amazon

In this article I wanted to introduce another nice, tiny, handy feature – unique constraint in SV. To give a background, consider a classical crossbar switch:

 

While every CPU can talk to/access every memory, for every access uniqueness must be maintained in terms of one-to-one connection. This is usually referred to as “Uniqueness Constraint” (ref: http://www.wonko.info/ipt/iis/infosys/infosys5.htm). In SV 2012, with unique constraint feature one may code a transaction model for this as:

 

 

One could perhaps combine this with a foreach and make it more elegant etc. But the bottomline – the unique constraint is really handy at times!

Welcome SV 2012/2013 :-)

Now our training in VSV (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) can cover this as a lab exercise – make sure you enroll in a session to learn more! See: http://www.cvcblr.com/trainings for more!

Technorati Tags: SystemVerilog,EDA

Help yourself & UVM community by sparing few minutes – Verilab’s UVM survey

 

UVM Runtime Phasing and Phase Jumping Survey

If you are well aware of UVM runtime phasing/phase jumping issues, quickly help yourself and the UVM community at large by filling out this survey:

• Verilab UVM Phasing Survey

Now for a background and for those who are “undecided” whether or not I have an issue with it, here is more information:

One of the significant updates done to OVM while bringing up UVM as the standard for verification methodology was the phasing. (For a detailed paper on user issues with OVM phasing approach, see: http://www.synopsys.com/community/snug/india/pages/abstracts.aspx?loc=india&locy=2011 and https://www.synopsys.com/news/pubs/snug/india2011/TA1.2_Intel_paper.pdf)

As with any standard development, there are differing view points coming from various experts, users etc. around the globe.India being the most vibrant Verification geography, it is very probable that many of the verification leads here face these problems day-in and day-out. So why not speak up and help us fix the UVM phasing the way YOU would like it?

Verilab, a premier verification consulting firm based in the US is conducting a survey to find out whether UVM users are currently taking advantage of runtime phasing and phase jumps, and if so, whether or not they would be impacted by certain changes the committee might propose.

So in case you are an active user of UVM, please spare a few minutes and take the survey at:

• Verilab UVM Phasing Survey

Technorati Tags: UVM,EDA,VIP

Upgrade yourself to SystemVerilog 2012 – our SVA handbook, 3rd edition is published!

They say “innovation never stops” – it is true for the SystemVerilog language committee. And it is very true for our co-author Ben Cohen, who even at the retired age keeps updating himself on latest on SV, VMM, OVM, UVM and of-course SVA. Ben Cohen is the Accellera nominated representative for the SV-AC committee on IEEE dev team.

See TOC at: http://systemverilog.us/SVA3rdE_preface_toc.pdf

The cover of this book is a NASA photograph of Mars, taken by Curiosity. Just like how Mars is enormously big, the verification state space of most of the modern day designs are extremely large. While there have been several advances in the area of "stimulus" or "activation of potential design errors", the amount of checking being done during such activation (either via simulation or formal analysis) demands detailed, precise design specification. This is precisely where SVA fits in the design flow. Just like how the whole world awaits pictures & findings from Curiosity to learn more about Mars, SVA could be used by the design verification teams to learn about the functional quality of designs.

Here is what the forewords say:

Dennis Brophy Director of Strategic Business Development, Mentor Graphics.

 

In 2010, research showed use of SystemVerilog was up more than 233% over prior years with more than 7 out of 10 design and verification engineers using it. Even more telling was the use of the SystemVerilog Assertions (SVA) part of the standard. Research showed that assertions enjoyed the same high level of use with 7 out of 10 design and verification engineers adopting SVA.
Assertion based verification (ABV) methodologies has been found to address design and verification challenges and the market use reflects it. The assertions portion of the IEEE SystemVerilog standard has also been enhanced over these years to extend and improve what can be done with them based on the cumulative experiences of the design and verification community to date.

The third edition to the SystemVerilog Assertions Handbook comes at a time when the IEEE updates its popular SystemVerilog standard and at a time when the FPGA community is increasing its adoption of SystemVerilog assertions as well. Design and verification engineers will find the handbook useful not just as a resource to begin to adopt assertions, but to apply the latest additions and updates found in the IEEE standard to the ever pressing design and verification challenges.

 

 

Sven Beyer, Product Manager Design Verification, OneSpin Solutions

http://www.onespin-solutions.com/

The SystemVerilog standard itself has been very much alive with two updates in 2009 and now in 2012, enhancing many existing features and adding numerous new ones. So more and more engineers are exposed to SVA while at the same time, the standard quickly evolves, trying to address the growing needs of those engineers for more productivity. This definitely calls for a first class reference documentation – and this book, SystemVerilog Assertions Handbook, 3rd Edition by Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari, and Lisa Piper, provides such a comprehensive reference manual that is suited for both SVA power users and novices. It introduces assertion methodologies and gives a clear idea on what assertions are good for,addressing both coverage and the complementary strengths of dynamic and formal verification. It carefully
lays out the numerous SVA language constructs one by one in a way that really gets across to the typical engineer, emphasizing the intended usage, adding telling examples, and listing the counter-intuitive pitfalls that may cost an engineer precious time in debugging. Therefore, this book is sure to find its place on the bookshelf of numerous engineers all over the world, and since it is the first comprehensive reference manual to also address the IEEE 1800-2012 standard, for example with its numerous enhancements to the checker construct, it is sure to remain on this shelf and be extensively used for quite some time.

 

Stuart Sutherland , SystemVerilog Training and Consulting Wizard
Sutherland HDL, Inc.
http://www.sutherland-hdl.com

The complexity of the design we need to verify requires that an assertions language has a robust set of features and capabilities. The SystemVerilog Assertions (SVA) language meets that rigorous requirement. The robustness of SVA also means that it can be challenging to learn to use SVA -- and to use it correctly. The SystemVerilog Assertions Handbook is an essential resource for overcoming that challenge. The book examines the use of SVA in the context of verifying true-to-life designs. Thorough explanations of each feature of SVA show the where and how to use SVA correctly, as well as point out pitfalls to avoid. At my company, we feel this book is so essential for understanding and properly using SVA, that we include a copy of the book as part of the standard training materials in all of our “SystemVerilog Assertions for Design and Verification Engineers” training workshops.

Cristian Amitroaie CEO, Amiq

.

The first benefit this book brings is a systematic and clearly organized perspective on SVA, from planning to terminology, from how assertions work and how to debug them, to coverage driven and formal verification using assertions. This includes the language clearly identified rules, and many tables and figures annotated with comments.

Second it offers many concrete examples. Examples are fresh air for engineers when diving into complex topics and this book has plenty, including the mapping between natural language and the corresponding SVA implementation.

Third, it contains guidelines on what to use and what to avoid, based on experience with both SVA and UVM. Knowing and following best practices are essential to engineers these days, when work pressure doesn't leave much time to carefully digest all the implications of the highly sophisticated means we use on a daily basis.

This is a book every engineer should keep handy!

Technorati Tags: SVA,Assertions,SystemVerilog Verilog EDA

Visualizing SystemVerilog event regions

One of the strengths of assertions in SystemVerilog is its well defined sampling semantics. Though it works out-of-the-box and is robust, many users don’t seem to understand it in depth. As we have been blogging on assertions – one needs to be very “pedantic”, i.e. detail oriented to be able to appreciate it, demonstrate it and understand it.

We at TeamCVC have been pioneering assertions as a focus area since our PSL book days (end of 2003, http://www.systemverilog.us/psl_info.html) and it has been almost a decade by now! We cover this in all our training sessions on assertions such as:

• SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf
• PSL: http://www.cvcblr.com/trng_profiles/CVC_LG_PSL_profile.pdf

Even during our popular VSV course (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) we touch upon this topic during the program block discussion. Below is an extract from our training/book on SVA (http://www.systemverilog.us/sva_info.html):

 

 

While the above slide goes well into the depth of this topic, often users ask us if they could “visualize it” inside waveform. Recently we did a SVA class for a VHDL customer who use Questa. Being part of QVP http://www.mentor.com/products/fv/partners/qvp we at CVC have access to Mentor’s latest technologies and this customer insisted that we use Questa during the labs. We enabled more debug sessions including their famous Questa ATV (Assertion Thread Viewer) feature. One of the nice examples our TeamCVC have created explains the events/time-regions nicely. See below for a screenshot:

 

It is almost the same as SystemVerilog LRM’s event Queue – brought inside the waveform, isn’t it! Here is a code snippet for the RTL regions such as “ACTIVE, INACTIVE & NBA” – this is same as in plain Verilog BTW:

 

Now recall that in testbench with System Verilog there is a program block that executes in REACTIVE region. And so are the assertion action-blocks. And within program block one can do blocking, #0 and NBA ssigns. So how does that get scheduled?

 

And relevant code-snippet for the REACTIVE assignments:

 

 

Putting the full waveform:

 

NOTE: the “time” doesn’t advance, it is only the DELTAs – Questa is powerful indeed in visualizing it, we will try and add other tool screenshots in near future if there is enough demand from you – our beloved readers!

Before we close, here is what a full, IDE (Integrated Development Environment) that Questa provides for this:

Hope you enjoyed this “flow of events” and the power of “visualizing” it – as much as we did. Drop your comments below!

Signing off with confidence, it is TeamCVC!

Technorati Tags: SVA,SystemVerilog Verilog EDA,Verilog,EDA,Questa,Debug