From a fresh grad to VLSI Design engineer – Meet Mr. Kaleem, Sasken

 

They say the best appreciation one can get is through one’s customers’ voice – we at CVC (www.cvcblr.com) take every individual trainee as serious as our corporate customers. That has been our reason behind success on both Corporate & individual levels. Here is yet another success story, this time from Md. Kaleem, ASIC Design-Verification Engineer @ Sasken. Kaleem got trained by TeamCVC and also was consulting for us for 2 projects after the training, through which he gained real practical knowledge that has helped him sail through the tough job climate. Kaleem went through our EIC (http://www.cvcblr.com/trng_profiles/CVC_EIC_profile.pdf) and then worked on OVM http://www.cvcblr.com/trng_profiles/CVC_DR_OVM_profile.pdf projects before moving on to even better job prospects.

Here is what he wrote to us over this weekend! Good luck Kaleem and keep in touch!

Mohammed Kaleemulla (http://in.linkedin.com/pub/mohammed-kaleemulla/23/186/b98)

Sent: Sunday, January 16, 2011 12:23 PM

Hi,

Sir This is Kaleem here,i have got a job in Sasken for the post of design verification engineer,I thank CVC for giving me all the support required for developing  the technical and knowledge-able skills, without which I wouldn't have  reached here and I hope we will have a reciprocate communication.

Regards
Kaleem

SystemVerilog constraints – distribution & using FCOV to visualize the effect

– Satish U, ASIC Design & Verification engineer @ CVC (www.cvcblr.com)

Every day at work is learning something new. More so when you are asked to work deep into advanced technologies such as SystemVerilog. In a recent project I was asked to delve deep into the constraints portion of SystemVerilog and solve few customer problems in modeling real life traffic pattern generation using SystemVerilog constraints. As part of it, I came up with an interesting to way to visualize the distribution through SystemVerilog covergroup/coverpoint. Though it is little round-about and may not be the best way to “verify” distribution, the technical lead at CVC quickly grasped the value and encouraged to explore more and develop a blog on the same. It is this “cultivating ideas” that makes working at CVC (www.cvcblr.com) a perfect blend of learning & fun (and don’t miss it – very aggressive timelines too).

 

                  A New way to check the distribution

  By definition the distribution within randc must be uniform. Let’s formulate this statement and validate the same. To find the distribution of lets say randc within a particular range N (N is the number of values in the range). Now let us assume M is the number of times an object is randomized.

Each value has a probability of 1/N.
 

• Case1: IF M = 1*N - If M= N then the values should be unique without any repetition.
• Case2: If M = 2*N - each value should be generated 2 times.
• Case3: M = K*N. Hence the number of times each value shall be generated is equal to K.
  

The N & M determine the “stimulus” side of verification. How do you “check” the distribution? An automated & robust method would be to use a queue and check the contents of the queue to see if they are unique, Infact one of our interns (Suhas: http://in.linkedin.com/pub/suhas-reddy/15/b02/49) is doing this as a mini-project at CVC (www.cvcblr.com) as part of our popular BUDS internship (http://www.cvcblr.com/downloads/BUDs_CVC_Acad.pdf).

However I proposed another interesting way to do this: Declare X as a cover point within a covergroup , so by default we will have N bins created for the N number of values (else one could use the auto_bin_max if care to). Other choice would be to use an array bin as shown below.

To demonstrate with an example:

`define N 4

`define K 1
`define M `K ** `N

`define seed_value 100

package pkg;
class xactn;
  randc bit [(`N-1):0] a;

  covergroup cg;
   A_cp      : coverpoint  a { bins a[] =  {[0:15]};}
  endgroup:cg
   function void post_randomize;
     cg.sample();
   endfunction

lets assume a 4 bit vector a, So we can have 16 possible values (N = 16).

We used Aldec’s (www.aldec.com) Riviera-Pro:      

Here is how Riviera visualizes it in its coverage report.

 

• Case1: for M = N if all the bins are hit once it means that i have uniform distribution.
• Case2: M = 2 * N - each bin should be hit 2 times.
• Case3: Now lets take the constant 2 as K. the equation becomes M = K*N. Hence the number of times each bin is hit will
     be equal to K.
  

We used this method to analyze various constraints and distributions. More about it in part-2 of this blog. Stay tuned to VoW blog! 

Mentor’s User-2-User conf is nearing – have your Qs answered through John Cooley!

If you haven’t registered yet, goto:

http://user2user.mentor.com/bangalore-india-2010.html 

With Wally Rhines speaking, you can’t afford to miss his power-packed keyonte. Also this year there is Mr. John Colley of www.deepchip.com presenting a session. Known for his open, user-focused comments on various tools, technologies & vendors (sometimes creating controversies too) this is one session that’s worth beating Bangalore traffic to be there!

BTW, John is also looking for good survey questions focused on Indian audience and issues concerning Indian users of Mentor tools. So do send them across via www.deepchip.com 

See you there at Mentor’s U2U on Dec 10th. Look for TeamCVC (www.cvcblr.com) in the crowd and we can chat!

TeamCVC,

www.cvcblr.com/blog

Increased user momentum at CDNLive India

Quick summary of what I liked at recent CDNLive India. Read live tweets @ www.twitter.com/cvcblr

First of all, the venue is FRESH – ITC Royal Gardenia hotel, a welcome change from regular Leela/Taj :-) Second, the first few sessions were JAM-packed with more than 25 customers standing (with all seats occupied). This was surprising as the audience beta the Bangalore traffic to be there at around 9.30 AM.

On the technical front, well let’s focus on what we know best – Front-end Design & Verification. Frankly – I was not alone who got totally confused about which “Verification” track to choose from. There was this

• “FED + Verification track”
• System Design & Verification track

I first though it was the FED that I should be in, as it contained one of my much awaited Nokia paper on Formal/ABV/IFV usage. But my good friend @CDN Maruthi Srinivas helped with clarification. His explanation:

First of all sorry for confusion, this year we had so many good papers on Verification and we had to fit as many as we can. We decided to move some of the Formal/ABV papers to FED track. The core Verification papers are on the Track-V

Now being @ the common session, John Bruggeman did an excellent job with his EDA360 talk. With so much being tweeted about it, honestly I got little saturated prior to his talk. But his talk truly rejuvenated the topic and his expressive demo revealed the vision well inside 3 slides. Kudos JohnB!

Next to see was TomAnderson’s Verification roadmap – strangely this was presented at Track-IV/FED. Luckily I was there in that track and as ever before, Cadence’s vision was great – especially linking the Conformal LP and Functional Verification/MDV is very thought provoking. The “Advanced Specman” was known to us at CVC http://www.cvcblr.com/blog/?p=173, but for many it was new there. And with similar capabilities being explored for SystemVerilog in the roadmap, there was enough for everyone to cheer about!

On the technical papers – a noted aspect that almost every attendee shared is – the quality and depth of these papers this time around was amazing. Be it the DFT Verif paper from TI (90 % of DFT logic bugs were caught by IFV flow), the TLM-e paper from ST-Micro and/or the Arch Model Verif with Specman by TI.

I personally enjoyed the Freescale paper on “Corner Case analysis with Formal”, to avoid repeating it, read more about it at: http://www.cvcblr.com/blog/?p=215 

Nokia’s Modem IP Verif paper was one of the best presented ones IMHO and Manish Goel did an excellent & upto-the point job of staying on target. There were enough audience questions in his session than many others and even another presenter from TI (He got the best paper award, didn’t get his name though) shared some of his views during those interactive discussions. This I felt was true “customer-2-customer” interaction happening live before a full room audience – something that the CDNLive team can be very happy about.

One of the best audience Q was raised during an Assertion paper (guess the TI one):

• “While IFV sounds great, user still needs to write those white-box assertions, is there any automation available”?

Though the presenter didn’t use this specific feature, the CDN rep/AE was quick to note that indeed IFV has the ability to extract certain classes of properties from RTL.

..and for those looking for more quality assertions, explore the partner technology of BugScope from NextOp: www.nextopsoftware.com

Realities of IP reuse, from Verification perspective

IP reuse, RTL/Design IP-reuse to be precise has been in effect for over a decade now, thanks to the time-tested RMM book, http://amzn.to/bI04yK and the extensive support of those rules/guidelines/policies by Lint tools such as SpyGlass, ALINT (from www.aldec.com), and recently Ascent (from www.realintent.com).

However while talking to a customer recently on their Printer SoC verification challenges, some interesting facts/stats emerged:

• Yes we reuse IPs, they are Si-proven, but…

New SoCs use these IPs in very different context leading to:

• Different configurations that were never used/tested/verified before
• Order of configuring these IPs can make-or-break the systems

The “ordering” was more interesting and in recently concluded CDNLive India, Deeapk from Freescale Noida presented an excellent paper on: “Corner Case Verification with IFV and assertions”. While much has been blogged about the recently concluded event CDNLive, this paper didn’t get enough mention – atleast not as much as it deserves IMHO. Deepak had 3 excellent case studies:

1. Order in which IPs get configured can make-or-break the SoC. Traditional Code cov can not locate it. His team wrote those assertions manually and used IFV to verify them
2. During Power Shutdwon if there is a pending interrupt to be serviced, after wake-up that interrupt was forgotten – a pretty tall order for traditional code-cov to catch it. True one could write a test – only if you had thought about it!
3. Clock control from PLL and other enables

All these are quality bugs, but hidden in the given module for more than 1 tapeout and used in customer designs. They get exposed only with modern use scenarios and hence is the stress on increased quality, hence the need for IFV.

While Deepak’s team has successfully demo-ed the 3 corner cases, arriving at them was by no means a small task. Also who knows, how many such hidden gems/bugs are out there yet to be caught?

So while IP reuse sounds old, the verification of them is by no means is a done-deal. Great for WE all – those love Verification as it presents a good challenge.

Now just before I close this entry, a quick preview of an emerging technology that is well poised to change this scenario for sure – by generating QUALITY white-box assertions automatically for YOUR designs:

Looking beyond the current tools, emerging technology such as BugScope from NextOp (www.nextopsoftware.com) can greatly assist in identifying such corners from your RTL design and current simulation runs. You just need to see a demo/webinar or read carefully their Whitepaper http://www.nextopsoftware.com/assertion-synthesis-assertion-based-verification-whitepaper.html to explore more.

Leveraging Social Media in VLSI/Semiconductor/EDA – the ecosystem way

As recent EDAC panel discussed the impact of Social Media in VLSI/EDA marketing (see: http://bit.ly/dzd3Ev) it is quite clear that one alone can’t make a difference, no matter how loud you shout – it is the collective ecosystem – of company-customers-partners that can make a win-win case in this new age marketing. Refer to Altera’s slide on that from http://bit.ly/dzd3Ev

Jim @ Altera says that it is the customer-to-customer interaction happening via Social Media that makes the bigger impact.

Given the post-recession ramp-up at many semiconductor houses, teams are very selective in investing/exploring/adopting new technologies and they are all looking for true success stories and real user views than just tool/feature updates.

Now looking at Karen @Synopsys’s views: it is the GEEK-2-Geek connection that she/Synopsys is bullish about to leverage on this new media.

While she quotes SNUG group @ linkedin.com, we found even more interesting stats with Verification specific groups such as VMM, OVM & all new UVM. The interesting fact about VMM linkedIn group is it is created and managed by partner (Ajeetha Kumari, http://www.linkedin.com/in/ajeetha) than the vendor.

VMM: http://www.linkedin.com/groups?home=&gid=147448 with some 780 members,

OVM: http://www.linkedin.com/groups?home=&gid=145498 with 1200+ members:

And the all new UVM: http://www.linkedin.com/groups?home=&gid=3092645 with 250+ members.

What really is important about this UVM group is it truly represents the ecosystem – with members from all EDA Vendors, partners and growing user base. See for yourself from the image below:

 

Another partner promoted group is SystemVerilog for Verification @ http://www.linkedin.com/groups?home=&gid=1924084

Among these groups the number of jobs being discussed truly reflects the close relevance of these to the real engineers out there and it is quite clear that all have enough to benefit from it.

So let’s embrace the new Social Media and look forward to exciting times ahead. If you want to learn more about how companies can benefit from this Social Media, do not miss the latest edition of Entrepreneur  magazine in India http://entrepreneurindia.in/ – it has cover story on Facebook founder.

And here are some of our local enthusiastic bloggers/tweeters – am sure I have missed several, feel free to submit them as comments, I will add them to this ever growing list!

http://www.twitter.com/cvcblr 

http://www.twitter.com/pradeep612

http://www.twitter.com/sricvc 

http://www.twitter.com/am_its 

http://www.twitter.com/testbench_in

http://www.twitter.com/punechips

SystemVerilog Assertions for VHDL

It is becoming more and more popular to find users writing SVA for VHDL too – though the VHDL-2008 has PSL inside it and most of the EDA tools (Aldec, Cadence, Mentor & Synopsys) have good support for PSL-VHDL.

Recently a customer asked:

"The SVA binding port mismatch error only when I bind an VHDL output port to a SVA input port. But, when i bind a Verilog output port to a SVA input port, it compiles without a problem ".

  While it does look like a tool-specific issue, in old VHDL, an output port can’t be read, need a buffer type for the same. When you bind a SVA to a VHDL output port, SVA tries to “read” it.

It is a subtle issue – though many tools have relaxed this “semantic” check on VHDL side. Also VHDL-2008 allows reading of output ports IIRC. Check with your EDA vendor if you see this issue, they ought to be supporting it already!

Cheers

TeamCVC

www.cvcblr.com