Certificate course on Functional Verification …basics to ASIC verification using SystemVerilog

CVC is about to launch a 10-day certificate course on Functional Verification covering SystemVerilog in depth. Broadly it covers the following topics:

• Comprehensive introduction to Functional Verification (CFV)
• SystemVerilog basics (SVB)
• SystemVerilog Assertion (SVA)
• Verification Using SystemVerilog (VSV)
• Verification Methodology (VM)

Duration

Here is a detailed breakdown of the course with duration. Note that we have several “mini projects” tightly embedded in the course that helps in mastering topics learned so far in the course. This is on top of the regular labs that are part of the training. The detailed breakup of topics and labs is covered in next sections of this proposal.

Topic	Duration
Comprehensive Functional Verification	1.5 days
Mini Project I	0.5 day
SystemVerilog Basics	0.5 day
SystemVerilog Assertions	1.5 days
Mini Project II	0.5 day
Verification using SystemVerilog	2.0 days
Mini Project III	0.5 day
Verification Methodology	2.0 days
Project IV	1.0 day

Schedule

Tentative: Feb 09-Mar09

Contact

Send an email to: cvc.training@gmail.com and/or training@noveldv.com for more details, cost etc. Or call us at: +91-9916176014