An absolute *must read* for all those CDV/CRV fans (FWIW: CDV – Coverage Driven Verification, CRV – Constrained Random Verification):
http://www.deepchip.com/items/0479-05.html
A live case study from Jim @QCOM. It has good details about the setup, work done and results. Looks like nuSym does deliver the kind of promises/claims it makes, good going indeed! Based on the last 2 such results (both @deepchip.com) I have few observations:
1. Both of them were using Vera against SystemVerilog. While the technology shall be language independent, it will be good to get a SV case study out as well
2. I’m not very clear why and how nuSym can replace a core “simulator” – there are just lot more things in a “simulator” than just “coverage closure/intelligence” – what about debug, stability, memory footprint, gate level/ASIC sign off, dumping, Debussy like integration etc etc.? I fully appreciate the smartness in random generation – it is time EDA folks did that in so called modern “Verification platforms”. But I fail to see how a point tool like nuSym can “replace” a simulator, instead it shall augment it and bring the bigwig EDA vendor pricing down to a reasonable bargain :-)
More notes as we read/re-read that article.
Anyway thanks Jim for sharing those wonderful details!
Cheers
Srini
CTO @CVC www.noveldv.com
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