Sunday, February 1, 2009

Week long fest on Verification Using SystemVerilog - Bangalore

 

Quick facts
When: Feb 2 to Feb 6 2009

Cost: Rs. 5000 /- per day

Contact: cvc.training @ gmail.com, +91-9916176014, +91-80-42134156

What’s SystemVerilog?
IEEE 1800, SystemVerilog is the de-facto language for Digital system Verification (and Design). Almost every ASIC team is either using it or plan on using it in the next project! It is a major extension to Verilog-2001, adding significant new features to Verilog for verification and design. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of complete Object-Oriented paradigm features.

What’s a week long fest?
A week long fest on SystemVerilog for Verification is aimed at introducing SystemVerilog in its full capacity covering basics, assertions, testbench features and ending with methodology. At the end of this fest the essential features of SystemVerilog shall be covered and will enable you develop complex testbenches using advanced techniques such as OOP, Constrained Random Verification and Coverage Driven Verification.  It is aimed at novice SV users and hence language is dealt with a target DUT in picture. The goal is to put SV to use for real life verification than understand the nitty gritties of the language from semantic/gotchas perspective.

Who should attend?
Practicing Design and Verification engineers with tight project schedules are ideal attendees. DV managers will equally find it useful as they can grasp the complexity of SV. Though it is strongly recommended to attend the whole 5 day fest, some may choose just the assertions/testbench/methodology and be present in those days accordingly. Please call use for more details.

Tools used

  • Questa/Modelsim (Mentor)
  • VCS (Synopsys)
  • Riviera (Aldec) - optional

What’s the cost?
The basic cost of this course is Rs. 5,000 /- + ST (12.36 %) per day per attendee.

Terms & Conditions
· In general we require that the fee is paid in 100% prior to the start of the training.
· For large corporate with more number of attendees to account for their internal process we do allow an exception to the above rule; however we charge an additional 25% of the training cost per attendee in such cases. In case the fee is paid after the training, the payment should be made within 1 week after the training is delivered. Any additional delay shall be charged at 10% every additional day.
· Any "offer" price mentioned in the course announcement is applicable only for individual attendees and not for corporate.

Cancellation Policy
Course tuition is fully refundable up to one week before the class starts. Cancellations within a week (2-7 days) of the class start date will incur a 50% cancellation fee. Those who cancel fewer than 2 days prior to the class will be billed for the full amount of the tuition. A no-show will be treated as cancellation and no refund shall be given. For genuine cases of absence, we can provide a training token that the trainee can avail in one of the future training classes subject to space availability.

How do I register for a class?
To attend this class, confirm your registration by sending an email to cvc.training @ gmail.com. +91-9916176014, +91-80-42134156

Please include the following details in your email:
Name:

Company Name:

Official Email ID:

Contact Number:

Trainer Profile

Srinivasan Venkataramanan, CTO

http://www.linkedin.com/in/svenka3

  • Over 12 years of experience in VLSI Design & Verification
  • Co-authored leading books in the Verification domain.
  • Worked at Philips, Intel, Synopsys in various capacities.
  • Presented papers, tutorials in various conferences, publications and avenues.
  • Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV and OOP for Verification
  • Holds M.Tech in VLSI Design from prestigious IIT, Delhi.

Ajeetha Kumari, CEO & MD
· Has 8+ years of experience in Verification
· Co-authored leading books in the Verification domain.
· Presented papers, tutorials in various conferences, publications andavenues.
· Worked with all leading edge simulators and formal verification(Model Checking) tools.
· Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDVand OOP for Verification
· Holds M.S.E.E. from prestigious IIT, Madras.

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