At DVCon Accellera released its latest standard for VIP interoperability named UVM – Universal Verification Methodology.
12+ vendors demonstrated their commercial solutions around UVM – hasn’t happened for a long time in the industry around single standard – except perhaps for SystemVerilog itself (back in 2003?)
While the technical details can be talked for very long time, here is a practical, real-life experience of “waiting for too long to have this standard”. This could be your simple means of convincing your technical management why they should be looking at UVM seriously in next project.
On the DVCon evening (Mar 1st) I was having dinner with a good old friend of mine, Mahesh. Here are his experiences/pains of working with various verification projects for the past 6+ years:
Mahesh –
it was a nightmare 5-6 years ago for Verification engineers – you move from one project to another within the SAME company (for instance acquired companies in a large company), your way of work – a la - “methodology” changes, hell! How I write my BFM, how it interacts with rest of the environment, how do I control my number-of-transactions etc. etc.
And when you switch jobs – almost guaranteed to go through the unlearn-learn cycle. While this cycle is good in many-a-context, but not to do the same thing – in this case “verification” – just with different base classes/languages.
He was listing: e, OpenVera, SystemVerilog languages and eRM, RVM, VMM, AVM and the likes..include OVM if you move the timeline little closer to 2011 :-)
So having a standard methodology is certainly promising for end users and for management to manage resources across projects. Sure there are more compelling technical reasons too – hopefully all for better, but the good things is, even if there are some shortcomings, it is a platform to add things to and bring it to Accellera to grow it beyond UVM 1.0.
Here is a snapshot of what CVC (www.cvcblr.com) has to offer for you around UVM – UnleashingUVM
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