SVA: Endpoint detection in sequences

This week has been a great start for TeamCVC as we have had one of our best SVA training attendees from a local customer with solid, “pedantic” Design & Verification engineers attending the same. We at CVC cherish challenges and always prefer customers who keep us on our toes (than just a dull set of trainees who sit and “listen” all day along).

During some of the advanced SVA part of the slides, we showed the endpoint detection mechanism in SystemVerilog Assertions. To put it simply – an endpoint is an instantaneous result available at every-clock (or sampling event) vs... a temporal sequence is typically few clocks in length. In what followed as a good discussion we explored various forms of code.

Drawn from our popular SVA book (2nd edition, http://www.systemverilog.us/sva_info.html ), here is a slide with code contents.

 

Alas – we didn’t have a running simulator on the laptop connected to the projector during the training, it became little hard to “visualize” the waveforms. We promised the customer that we will revert back with a demo code and screenshot – and here is what we came up with  -after a tiring day at CVC – we still don’t call it a day until we satisfy our commitments! Here you go with the screenshot below:

Basically we have a sequence that reads as:

 

 

Now consider that we have 2 assertions, one with the entire sequence and the other with endpoint detection:

 

 

And to make it even more clear, let’s do the same in the consequent part as well:

 

Here is what the trace and results look like; Note the “LENGTH” of the threads with and without the endpoints – after-all “endpoint” is a BOOLEAN result, it had to be “short-lived” :-)

 

Feeling satisfied (for the day), let’s now call it a day from TeamCVC. And yes, a Very Happy and PROUD Independence day for all Indians!

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