As in any business, there are always lead players and those who try to “mimic” them. We see our trainings also the same way – let’s admit there are few players in this game in our region. However what sets us apart from the rest? Few:
1. First of all we serve the whole industry at large:
- Be it a fresh graduate (via our EIC: http://www.cvcblr.com/trng_profiles/CVC_EIC_profile.pdf, http://www.slideshare.net/svenka3/anubhuti-engineering-incubation-centre-eic)
- An experienced, mid-career engineer looking to re-skill, recently SystemVerilog being the runaway success (http://www.cvcblr.com/trng_profiles/CVC_VSV_WK_profile.pdf)
- Engineering managers, marketing execs who want 10,000 foot view of the VLSI ball game
- Sometimes, engineers from other domains (SW, Mechanical – yes we had one!!) willing to learn basics of Verilog.
Such a wide coverage of audience is very rare if any, even across globe. Again note that many may promise, it is important to deliver and that too with passion and from real experts, who can be named, identified than those typical “interact with industry experts” kind of statements!
As one of our testimonials (http://www.cvcblr.com/testimonials) go:
"...have been practicing for many years just what they teach now. A giant step in the right direction to introduce a quality VLSI design and verification in India!"
Sunil Kakkar, Chief Architect - SKAK INC.
2. We believe in what we do – yes we do NOT cover the whole VLSI flow – every wonder why? Espeically given that other training institutes here do claim that as a BIG deal? Recently an Aldec engineer (Purushottham) here said this:
I wonder why anyone would want to “specialize” on the whole VLSI flow, a typical ASIC/VLSI engineer works for several years on a specific role – either front-end or back-end, and not on both.
At CVC, our belief is that we should create employable talent pool than just some diploma, certificate holders. We infact receive several such resumes for our TDG division from other institutes, recently we had one – someone who is teaching Verilog at an institute, when asked to write some code and add “comments” used “ \\ Verilog comment “. Nothing against any specific individual or org, but just to reflect the state of what we saw.
Indeed I’m grateful to such experiences – that made us to realize the need for our EIC – an incubation center than just a training institute.
It is our genuine interest to place all our trainees – be it freshers or experienced ones – either through our industry contacts/existing customers or internally for our consulting projects. But we have very high levels of quality requirements to be placed – right from code indentation, linting, synthesis to verification. Unless the design, coding, tool usage everything measures upto our quality standards we just can’t hire folks into our TDG – we make that explicit every time we get a chance and NOT at the end alone!
So – to summarize, we BELIEVE in what we do, so if you are looking for a successful career and are willing to put in sincere efforts on your own, come and contact us training@cvcblr.com
Thanks for reading!
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