If you are involved in functional verification I am sure you have atleast heard of System Verilog as the IEEE standard. The first IEEE standard was released back in 2005 and went in for a revision during 2009. Now there is yet another major update – 2012, expected to be fully ratified by early 2013 (on time for DVCon 2013). Here is a nice blog on this: http://blogs.mentor.com/verificationhorizons/blog/tag/ben-cohen/
A major part of this new version is all about assertions/SVA. If you need a detailed list of changes and examples, with applications – look no further, get hold of our new SVA 3rd edition @ SVA book 3rd edition @Amazon
In this article I wanted to introduce another nice, tiny, handy feature – unique constraint in SV. To give a background, consider a classical crossbar switch:
While every CPU can talk to/access every memory, for every access uniqueness must be maintained in terms of one-to-one connection. This is usually referred to as “Uniqueness Constraint” (ref: http://www.wonko.info/ipt/iis/infosys/infosys5.htm). In SV 2012, with unique constraint feature one may code a transaction model for this as:
One could perhaps combine this with a foreach and make it more elegant etc. But the bottomline – the unique constraint is really handy at times!
Welcome SV 2012/2013 :-)
Now our training in VSV (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) can cover this as a lab exercise – make sure you enroll in a session to learn more! See: http://www.cvcblr.com/trainings for more!
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