Help yourself & UVM community by sparing few minutes – Verilab’s UVM survey

 

UVM Runtime Phasing and Phase Jumping Survey

If you are well aware of UVM runtime phasing/phase jumping issues, quickly help yourself and the UVM community at large by filling out this survey:

• Verilab UVM Phasing Survey

Now for a background and for those who are “undecided” whether or not I have an issue with it, here is more information:

One of the significant updates done to OVM while bringing up UVM as the standard for verification methodology was the phasing. (For a detailed paper on user issues with OVM phasing approach, see: http://www.synopsys.com/community/snug/india/pages/abstracts.aspx?loc=india&locy=2011 and https://www.synopsys.com/news/pubs/snug/india2011/TA1.2_Intel_paper.pdf)

As with any standard development, there are differing view points coming from various experts, users etc. around the globe.India being the most vibrant Verification geography, it is very probable that many of the verification leads here face these problems day-in and day-out. So why not speak up and help us fix the UVM phasing the way YOU would like it?

Verilab, a premier verification consulting firm based in the US is conducting a survey to find out whether UVM users are currently taking advantage of runtime phasing and phase jumps, and if so, whether or not they would be impacted by certain changes the committee might propose.

So in case you are an active user of UVM, please spare a few minutes and take the survey at:

• Verilab UVM Phasing Survey

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