Sledgehammer to crack a nut? – Use right tools for right class of design errors/bugs

I am sure you have heard this phrase before – “A sledgehammer to crack a nut”; the below picture describes it all!

Would you use a HUGE hammer to crack a small, tiny nut?

(If you are further interested in this phrase read: http://www.phrases.org.uk/meanings/sledgehammer-to-crack-a-nut.html).

I recently had a small design error introduced in a piece of  RTL as below: It is an interrupt masking logic, code snippet as below:

Note the use of “ANDing” logic – simply, AND- mask with data to produce result.The subtlety in Verilog/System Verilog is that you have 2 seemingly similar operators for doing AND operation;

1. The logical AND: &&
2. The bitwise AND: &

Given the “loose” data type checking, assignment rules etc. one can get away by using either one of the above many-a-times. In the above case the user used:

  result = data && mask;

With result being a vector the above is a “logical/design error” but usually a Verilog compiler would let this go through (as it is not an error as per LRM).

Now one can “verify” this by writing a testbench, simulate, look at waveform and debug. Depending on luck and the expertise of the engineer, it could take some 30-minutes to few hours. But as a Verification power-house CVC suggests to rethink – use the right tool/technology for the right class of design errors. These are things that are very easy for a static verification technology such as HDL-Linting to flag in less than a minute.

For instance, let’s try the above code with a popular Linter – ALINT from Aldec (http://www.aldec.com/products/alint/).

 

ALINT has nice rule sets pre-packaged for various policies such as STARC (http://www.starc.jp/index-e.html). It produces the following:

 

This will trigger 2 rules:
  -  rule about logic operation having a vector operand
  -  rule about bit width mismatch in the assignment - LHS vs RHS.

ALINT: Warning: test.v : (4, 1): Module "top". "STARC_VLOG.2.1.4.5" Logical operator has vector argument(s). Use bit-wise operators for multi-bit arguments and logical operators only for 1-bit arguments. Level: Recommendation 1.
ALINT: Warning: test.v : (4, 1): Module "top". "STARC_VLOG.2.10.3.4" Assignment source bit width "1" is less than destination bit width "8". Upper bits of the right-hand side will be filled with zeroes. Match bit widths exactly to improve the readability of the description. Level: Recommendation 2.

 

Now from a business perspective too – this is a far better option for your management – usually LINT tools are far cost efficient than full blown SystemVerilog simulator(s) such as Aldec’s Riviera-Pro http://www.aldec.com/Riviera

So next time when you receive a RTL code to verify, do yourself a favor by running a quick Lint run before looking for “hard bugs” that demand popular, powerful techniques such as Constrained-random, coverage-driven, UVM based etc.

BTW – CVC offers training sessions (http://www.cvcblr.com/trainings) on Aldec’s ALINT and HDL-Lint in general. Contact us (http://www.cvcblr.com/about_us) to see how we can help your teams!

Happy Verification ahead!

UVM with VMM – first trial of true inter-operability

 

As noted in our recent blog article http://www.cvcblr.com/blog/?p=362 UVM is the first genuine step in the industry towards verification inter-operability. But it has a long way to go before all the VIPs get migrated to UVM – if they do. So there is a strong need to leverage on existing code base such as VMM, OVM & UVM.

Below is a code snippet that shows how we can use both VMM & UVM messaging schemes in same env/code base. As such the code is not magic, is it? But do watch below for the real MAGIC..

 

If not for the inter-op kit, the above code would spit the messages from 2 different schemes and make it very hard for end user to keep track, customize etc.

With UVM & VMM loggers being separate and not “inter-operating” the following user issues may arise:

1. Different formatted messages coming at different lines, making it hard, ugly to read, analyze

2. Complicating data-mining of log files as there are 2 different formats now in same log file

3. Error, Warning counts distributed leading to unreliable FAIL/PASS detection

4. Any customization done by user on formatting needs to be done multiple times

5. Sending to different log files not as easy as it involves 2 different base classes now!

 

Again there are more, let’s get solutions on the table. Here comes the MAGIC: With VCS, try:

The log file now combines the `vmm_note into `uvm_info “magically” and unifies it for the users!

 

 

There is much more to this inter-op kit, see: http://www.vmmcentral.com/uvm_vmm_ik/ 

 

Enjoy UVM and more..

Verification inter-operability beyond UVM

As industry gets ready for adopting UVM with SystemVerilog, there are several practical combinations that come to the fore. One of the important concerns is about the existing code base/VIPs that can be “reused as-is”, yet benefit from various UVM features. For instance consider a VMM based VIP being plugged into a new UVM based env. Several user requirements/expectations arise:

1. Can the UVM & VMM co-exist in same simulation?

2. Can we leverage on single messaging scheme – instead of both `uvm_error & `vmm_error counting on their own, how do we unify them?

3. Can UVM phasing control/synchronize the vmm_xacotr::start/stop_xactor?

4. How does the UVM-Objection work with VMM-Consensus?

5. How do we talk from VMM-channel to UVM components and vice-versa?

6.How does the UVM ACTIVE/PASSIVE mechanism control VMM xactors underneath?

7. Does UVM config mechanism affect the VMM, if yes, how, if not then what do we do?

I am sure there are more. But just enough to get you worried! Thankfully the problem seems to have been acknowledged by the EDA vendors and potential solutions have started emerging. For instance the recently released VMM/UVM inter-op kit from Synopsys is at: http://www.vmmcentral.com/uvm_vmm_ik/

 

Another common requirement from many customers is the ability to mix multiple modeling & verification languages with UVM. Cadence recently donated its version of UVM ML (Multi-Language) to Accellera for potential extension. This contains UVM-SystemC via TLM 2,0 and UVM-e for integrating IEEE 1647-E based eVCs to UVM. Though the industry has publically seen only Cadence’s Specman supporting IEEE 1647-E language, if John’s ESNUG were to be trusted (why not BTW?, see: http://www.deepchip.com/items/0495-02.html), it may be soon that all major vendors release E-support.

As noted in our recent blog, http://www.cvcblr.com/blog/?p=361 the upcoming 2012 year seems to be quite interesting for Verification technologies.

Reusing functional coverage from block to system level – LSI @ SNUG India

Last week at SNUG India, LSI presented a good paper on the topic of Functional Coverage reuse (See: http://www.synopsys.com/Community/SNUG/India/Pages/Abstracts.aspx?loc=India&locy=2011#TA1)

Challenges and Approaches for Functional Coverage in SOC Verification Environments
Manikandan Subramanian, Ron Jacob, Sasidhar Dudyala, Srishan Thirumalai [LSI]

This paper describes the complexity in using block level functional coverage at top level and pitfalls and approaches to aid reuse. This also describes controllability on coverage infrastructure from block level to SOC level and how UVM-EA helped in building the layered testbench infrastructure that can be reused.

What I really liked about this is the level of maturity that the SystemVerilog adoption that this paper indicates in India – while functional coverage is one of the top few powerful features in System Verilog, its adoption has been traditionally slower than what we wished. Especially with the boatload of features, knobs/options to control/fine tune, it is clearly one of those features that is waiting to be explored in greater detail. In this paper Ron laid out a nice architecture for “coverage reuse” across levels of verification. The architecture he & his team proposed can be captured into 3 classes:

• Config class – to configure “How much do you want”
• Coverage class – to capture “what and all you want”
• Coverage collector class – to sample the coverage points

In a way the last 2 points have been stressed by VMM for years, and we at TeamCVC have been recommending it to our customers for years.

Specifically during our popular System Verilog training sessions such as VSV (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) we compare this to an athletic race and describe how the “field meters” placed/planted in the filed actually measures the speed while the runners/athletes simply RUN RUn & RUN! 

 

Now compare this to a classical VMM environment:

The environment with all the components form the “field” while the “transactions” that flow through match the real “athletes”. It makes a lot of sense to plant the “measuring meters” (in this case the “coverage collectors and the coverage models” away from the actual transactions.

 

This is what Ron’s team experienced too. Though there are some ACC technologies such as ECHO in VCS that traditionally worked better (see: http://www.cvcblr.com/blog/?p=9) with transactions “embedded with covergroups”, VCS’s ECHO has come a long way and has supported VMM style covergroups as well.

The next big challenge that Ron addressed was the “reusability” and need to “control” the amount of coverage at System Level from block level. He had several good guidelines for the users, recommend highly to take down his paper and keep it handy at work! While some of the “sample_cov” overriding can be better done using SystemVerilog 2009 updates to built-in sample() function, a lot needs to be still done. For instance how do we override a full coverage model/covergroup/coverpoint/bins/cross etc. at System Level?

Ron’s approach was to add disable bits – yes, better than not having it, but it doesn’t scale up. Several years back Vera added such AOP/OOP style extensions to covergroups, but due to slow user adoption, this was never ported to SystemVerilog. Talk to Arturo Salz – friendly known as the “Father of Vera HVL” by many if you are interested.Basically the extensions are to allow things like:

• Add extra coverpoint/bin/cross
• Delete/drop a block level coverpoint/bin/cross
• Re-define the entire covergroup etc.

Now – where do we go from here – IEEE-SA invites sincere participation from end-users to set directions, drive language features/enhancements via active participation. See: https://mentor.ieee.org/stds-india/bp/StartPage to know more.

Meet TeamCVC at next week SNUG India DCE booth

If you live in India, specifically Bangalore and work in the field of VLSI, it is hard to miss the well attended SNUG event every year. Just like last year, this year’s SNUG hosts the popular DCE - Designer Community Expo  

http://www.synopsys.com/Community/SNUG/India/Pages/DCE.aspx 

TeamCVC (www.cvcblr.com) will be at Verification track booth and you are welcome to stop by for a range of surprises, quiz & gifts including our various books (www.systemverilog.us). TeamCVC also has a paper co-authored by our CTO Srini (www.linkedin.com/in/svenka3) along with Kishor @Intel and Amit @SNPS, see abstract at: http://www.synopsys.com/Community/SNUG/India/Pages/Abstracts.aspx?loc=India&locy=2011#TA1

 

What: OVM/UVM paper with Intel-CVC-SNPS: http://www.synopsys.com/Community/SNUG/India/Pages/Abstracts.aspx?loc=India&locy=2011#TA1

When: Thursday June 23, 2011, 10.30 AM

Where: Leela Palace Hotel

What: Meet TeamCVC @ our booth, DCE: Win books, gifts, take quiz etc.

When: Thursday, June 23
Time: 5:15pm - 7:15pm
Location: Grand Ballroom, Leela Palace

Verification gets another buzzword - “ADS” thanks to Cadence

At DAC 2011, Cadence introduced yet-another 3-letter buzzword to the wonderful world of Verification – ADS: Assertion-Driven Simulation. Traditionally assertions have been monitors/passive elements, but some high-end formal verification groups have been using it to drive model checkers, random stimulus generators etc. CVC (www.cvcblr.com) has a long history with assertions and we saw this ADS model first with a start-up named Safelogic in Sweden, that got acquired by Jasper a while ago. Under the hood most of the formal tools could do this – be it CDN’s IFV, SNPS’s Magellan etc.

Jasper rolled out ActiveDesign in 2010 and TeamCVC spoke to the developers and blogged it at http://www.cvcblr.com/blog/?p=132

Recently Zocalo (www.zocalo-tech.com) announced VisualSVA product that enables capturing of SVA via a GUI and also provide debug traces

And now Cadence brings it even more closer – down to your Simvision window – with a push of an additional button in your favorite Waveform window you get stimulus, see: http://bit.ly/mo9kjl 

This is certainly encouraging and will propel the industry to increase the much needed assertion density among legacy & new RTL designs to improve the quality of designs.

From a language perspective SystemVerilog 2009 added checker..endchecker and rand variables inside. While the 2009 LRM limits the checker to be “monitors” alone, the recent discussions in the SV-AC IEEE extension groups proposals are emerging to make them “generate random stimulus” from checker blocks too. So stay tuned for more on ADS :-)

An evening full of Do’s & Don’ts in OVM/UVM with Cliff Cummings

Clifford Cummings (http://www.linkedin.com/in/cliffcummings) is a crowd puller – no doubt. Consider:

• Hot summer mid-day (2 PM start time)
• Bangalore traffic/center of city (potential peak traffic towards end time of 5.30 PM)
• A venue known/infamous for a “HUGE” area but no so frequented by hi-tech community of Silicon Valley of India, past events over there had history of terrible attendance

Yet there were close to 70+ Verification engineers at Cliff’s UVM/OVM seminar aptly titled as:

“Advanced SystemVerilog Tips Including OVM & UVM Tips”

 

It was indeed for Advanced System Verilog users as he had most of the slides on OVM/UVM. TeamCVC (http://in.linkedin.com/in/cvcblr) specifically its trainees, some 11 of them were there cherishing their stint at CVC (www.cvcblr.com) as they hear a world-class seminar and being a fresh graduate, making sense out of that was  a pride on its own. That’s the power of CVC’s time proven EIC training (http://www.cvcblr.com/trng_profiles/CVC_EIC_profile.pdf) that takes in a fresh B.E/M.Tech graduate and turns them to be most sought out Verification engineer in local market.

Madhavi Rao of Cadence (http://in.linkedin.com/in/madhavirao) has done an excellent job in making the event popular and driving it to customers. TeamCVC did their bit, by blogging about it via: http://www.cvcblr.com/blog/?p=325 and also tweeted via: http://twitter.com/cvcblr – for those who believe (still) that Social Media is not engineers/hi-tech, there were more than 5 folks who told me at the event that they heard it via Tweets and they signed-in for the event!

Coming to the event technical content – A good detailed, 60-page write-up by Cliff is at: http://j.mp/gJegMP And for those who cherish/enjoy live-tweets, let’s not repeat all the hardwork TeamCVC had put in live-tweets during the event itself, see: http://twitter.com/cvcblr

The true success of the technical value was evident towards the end – during the High-Tea, almost every attendee had atleast one TIP to go home with (many with more than 1 obviously), I heard things like:

I would not use global_stop_request after run_test

I would not look at enable_stop_interrupt

etc.

Cliff cited JL Gray (http://www.linkedin.com/in/jlgray) for his interesting analogy of OVM’s TLM port-export to the famous Hollywood Blockbuster Avatar Movie. I am still looking for more details on that comparison as it wasn’t easy to catch that link during Cliff’s brief notes.

Cliff’s own explanation of port-export to a driving-a-car using steering-wheel was interesting as well.

Cliff’s session on handling end-of-test was the best pick in this event. Start with the following:

  initial begin : end_of_test_try

    run_test();

    global_stop_request;

  end : end_of_test_try

If you need more details, read: http://j.mp/gJegMP

It was indeed a nice evening with Cliff and other Verification geeks of Bangalore. Now, let’s look forward to how the Pune event goes, maybe http://twitter.com/punechips will provide us the live-tweets :-)

Spend 3 hours to know more about UVM, OVM with Cliff Cummings @ Bangalore/Pune

If you are curious about recently released UVM standard – you won’t have missed to note the DVCon-2011 blogs/tweets etc. Some of those captures can be seen at http://www.cvcblr.com/blog/?p=283 

http://www.cvcblr.com/blog/?p=298

http://www.cvcblr.com/blog/?p=322

Now, in case you didn’t visit DVCon, here is UVM coming to YOU – at Bangalore & Pune. Thanks to Cadence & QLogic, there are free UVM update events being scheduled on Apr 13th & Apr 19th. Register for free right away.

Agenda:

• New UVM 1.0 overview and comparison to OVM
• Important OVM and UVM phasing
• Secrets in mastering OVM and UVM
• Graceful termination of tests in OVM and UVM with emphasis on the objection mechanism
• Some of Cliff's favorite SystemVerilog tips and tricks
• Some early UVM techniques and best practices

Date	Time	Location
April 13, Wednesday	2.00pm – 5.30pm	Bangalore Auditorium 1 NIMHANS Convention Centre Hosur Road, Bangalore
April 19, Tuesday	4.00 – 7.30pm	Pune, MCCIA Auditorium A-Wing Ground Floor MCCIA Trade Towers (Building with Crossword Book Store) Senapati Bapat Road, Pune

Pune – the “Oxford of the East”, SystemVerilog and the vibrant community

Last week TeamCVC held a 4-day training on System Verilog at Pune – a pleasant city in the western ghats of India, also known as the "Oxford of the East" due to its vast student community & research institutions.

TeamCVC has been to Pune few years back for a VMM training, see some of those experiences at http://bit.ly/eHMaH7

But this visit has shown how fast this city has been growing and the recent boom it has been experiencing - atleast through an entrepreneur viewpoint. The first thing that struck me on my way to the hotel from airport was the flurry of developments – almost 90% of all hoarding/banners showing upcoming apartments, It is almost like Bangalore some 10 years back – with so many IT firms growing their staff strength, new office spaces being built etc.

The weather was pleasant, gets quite hot mid-day but then cool breeze in the evening, gets little cold during early mornings. Kind of similar to Bangalore, atleast for this period of the year.

The Hinjewadi area/IT park is amazingly clean, well maintained, with wide roads. Trafiic was sensible, a BIG sigh of relief for a Bangalorean :-) Though there are BPO vehicles plying along the roads, they are not as hars driving as their counterparts in Bangalore are.

Coming to the training folks, what really surprised me was the true cosmopolitan nature of the IT crowd there (from the general media projection of Maharashtra). There were folks from Andhra, Karnataka, Gujarat, Delhi and of-course Pune & around. The razor sharp audience kept the training truly interactive and alive. I generally have a higher image/perspective of Maharastrians when it comes to intellect and I wasn’t proven wrong, the audience were dot on time with labs, always had the enthusiasm for learning more – something that a passionate trainer would look forward to in each session. It is indeed a pleasure to have such attendees as connoisseur. It was a mix of few experienced folks and some fresh graduates, similar to our recent Cochin experience (Read: SystemVerilog Assertions Field-day). However, the biggest difference was that the attendees were finishing all labs on time and were asking for more stuff, pretty impressive talent pool indeed!

There were some good discussions around the SystemVerilog assertions – specifically on the Sequence repetition operators and the first_match. While we cover the basic repetition operators in our first session on sequences, we defer the first_match to advanced sequence session. One set of attendees finished the lab on sequences faster and started debate on "potential multiple matches" and the necessity of the consequent to hold for all matches. VCS DVE’s sequence debug/visualization came in very handy to appreciate the SVA behavior.

The discussion on $cast in SystemVerilog went on really nice, with new animation kicking in on demand and was well received. While the "syntax" was learnt the hard way, some folks weren't convinced on its real usage – not uncommon as the first level SystemVerilog course, we call it VSV () shows you how to use it, but our methodology sessions truly leverages it. Some of the tech-hungry attendees said "Yeah Dil Maange More.." and we quickly opened up $VCS_HOME/etc/rvm/vmm.sv and showed some of the real life usage of $cast – the instant reaction was "Oh My God – so common in reusable code.

Wanted to add more stuff, but realize it is already a long post, so perhaps some other time with few images to make it more interesting to read.

Powered by Qumana

What’s beyond UVM? - Excerpts from DVCon BoF panel

Last week at DVCon we had a very interesting Birds-of-a-Feather meeting on Mar 1st evening. Panelists included Tom Anderson from Cadence, Yunshan Zhu from NextOp and Adnan Hamid from Breker Systems.

 

It was moderated by Srinivasan Venkataramanan from CVC. See pre-BoF invite/details at:

http://www.cvcblr.com/blog/?p=272

The theme of this panel was “Verification Closure” – given that 2011 DVCon marked the birth/release of UVM standard for developing reusable, inter-operable VIPs, it was a perfect fit for a group of technocrats to explore what is beyond UVM. We had some very interesting discussions and here are some excerpts. If you feel I missed some discussion topic or have any comment on this, feel free to blog it here!

To start with, Rick Nordin of Breker Systems introduced the panel topic and the moderator.

                      

Srini (www.linkedin.com/in/svenka3) presented single slide setting the stage for the panelists and had the honor of introducing the esteemed panelists of the evening: Tom, Yunshan & Adnan.

Here is the slide from Srini:

Basically – we have the UVM now, how do we leverage and verify a complex SoC with it – what are the pieces of the puzzle involved beyond UVM itself? At broad level here are the key pieces:

• Tests/Stimulus – co-ordinated across several UVM VIPs/interfaces – this is far beyond regular SystemVerilog constraints, UVM sequences. Sure UVM’s virtual sequences can help, but with lot of coding and very little reuse from block to SoC level, see http://www.cvcblr.com/blog/?p=272 for some example.
• Targets/coverage goals – not just “code coverage” or “cross every possible input to every possible output” – rather “qualified”, identified and possibly filtered as per existing simulation runs – all automatic
• A robust platform to do the execution, track it in an executable plan and measure the progress

 

Tom presented first with Cadence’s solution of automated constraint automation, vPlan and integrating adjacent technologies such as Formal, Emulation etc. He was as grand as ever in his vision and covered a whole lot in 1-slide indeed!  Pircked it from Tom’s parallel blog on this topic: http://www.cadence.com/Community/blogs/fv/archive/2011/03/11/a-modest-proposal-using-formal-to-close-coverage-gaps.aspx

Then Yunshan presented how to automatically identify qualified coverage targets based on RTL + existing simulation run through NextOp’s Assertion Synthesis. This has caught lot of users excited about this technology and the emerging customer reports from companies like Altera (at deepchip.com) is only making the case more stronger! Here is a quick snapshot of what NextOp brings to the table in this space (from: http://www.nextopsoftware.com/Te_AssertionBasedVerification.html).

 

 

Yunshan also presented on how this fits nicely to today’s existing flows and extends the scope for formal/emulation on demand basis. This is extremely beneficial as the audience got to see that NextOp doesn’t really change the flow, rather fitst nicely to any existing flow and brings in value instantly.

Then it was Adnan’s turn to present his views and he started with a BANG! showing how “Model based stimulus-check-cover” generation helps in achieving Verification Closure. In his terms the “testcase generation” is incomplete if it talks “only” about the stimulus – instead it should capture the “stimulus, expect/checker and a coverage model” all in one. A grand idea in plan, call Breker to see how to make it true on your designs!

Then Adnan moved on to addressing the SoC level challenges in developing, C based tests with all desired bells-n-whistles such as:

• Reuse of IP level scenarios/graphs
• Automated C test generation
• Heavy memory coherency and
• Debug of such scenarios as-if it is plain SW code (via ubiquitous printf)

 

Perhaps too much to absorb in 10-minutes, but that’s why they had a booth at DVCon exhibit :-)

Then we had an exciting set of audience questions ranging from “explicit goals to hidden targets” (an interesting attendee posted it by taking examples from Hindu mythological characters such as Ravana & Indra – I will try and cover that in a separate blog on that for pleasure, if not anything else..). A quick summary of that question:

I am clear of an explicit goal to be hit by my SoC env (though it is not trivial to

hit it through simple set of “constrained random sequences” running on their

own, need a great deal of co-ordination).

But what about those “hidden/invisible” targets that are deeply buried inside

my huge RTL code base?

 

Ans: This is where "Assertion Synthesis” neatly plugs-in – given a set of simulation results, it goes into selected set of blocks/IPs, analyzes it and reports “quality properties” that the design + simulation exhibits. Now the user (typically the block owner) reviews those properties and marks these as assertions or cover holes. Sure there is work – but a targeted set of properties on potentially unstable/suspicious blocks/IPs with automated pruning of “redundant” stuff is a BIG deal indeed. Talk to www.nextopsoftware.com for more!

Some of the attendees:

There were some excited/over heated arguments about temporal properties vs. white-box ones, especially from Vibarajan (http://www.linkedin.com/pub/vibarajan-viswanathan/3/568/343P). The fact is existing System Verilog constructs do a great deal of  work for block level/IP level properties, but they fail to deliver at SoC level of abstraction involving class based transaction level behaviors. Sure one can do lot of code around behavioral checkers/scoreboards (and as my good friend Nitin puts it – aren’t you trying to use wrong feature for wrong problem? – I respectfully disagree on this).

Another interesting discussion was around reach-ability of various cover goals. The panel seemed to have the best answers given the abundence of talent/experience on the panelists. Tom explained how formal analysis can either reach them – even if they are hard to reach via regular constrained random generation. Tom also pitched in the role of “unreacahbility analysis” as some of the goals might be just NO-GO given the design constraints/logic and it is very hard to identify them manually. When it comes to higher level, system level scenarios there is this new Graph based scenario models that can literally “mind-map” verification intent thereby letting users “begin-with-end” in mind. You need to listen to Adnan to believe it, or better yet evaluate their flow to benefit from it!

Photos from this BoF courtesy Joe Hupcey are at: http://www.flickr.com/photos/24605532@N08/sets/72157626233541664/with/5513590114/

If you have any more comments/questions to the panel, feel free to add them here in this blog (http://www.cvcblr.com/blog/?p=319) as comments, I will try and get the panelists respond.

Extracts from DVCon UVM poster session – it is vibrant ecosystem indeed

Here are some snaps from recent DVCon UVM poster session. More than 12 vendors demonstrated their commerical offerings around UVM and it was an electrifying experience for the attendees/potential customers (some 180+ UVM tutorial attendees). Products/offerings broadly fell in the following categories:

• Simulators – Cadence, Synopsys (DOn’t recall Mentor on poster, but of-course Questa supports UVM), another missing poster EDA tool company was Aldec. Though both Mentor & Aldec had their booths at the exhibit.

Cadence had a poster on how IUS supports UVM and extended debug features targeted for UVM users. Here is Joesph H with his Cadence poster

 

 

Synopsys had a clear, simple poster on how VCS extends its leadership in SystemVerilog performance. Here is Adiel Khan explaining with passion to a customer Synopsys poster:

 

• Register model automation, maintenance: AgniSys dominated the poster with lots of visitors asking questions. Infact their poster attracted attendees even after the tutorial break was over and the session re-started. Alas, Anupam wasn’t there, but Srini from CVC (www.cvcblr.com) did some back-up for Anupam. Part of EDA ecosystem, Huh!

Here is Anupam explaining his poster to a customer potential:

Other similar offerings were demonstrated by Semifore & Doulog.

• Trainings: Clearly attendees were well treated by thriving training ecosystem – with CVC (www.cvcblr.com), Doulos and others showing off their new trainings on UVM.

 

 

• VIPs: CVC (www.cvcblr.com) launched its latest campaign around UVM aptly named “UnleashingUVM” with trainings, products & services around UVM.

Here is our CTO, Srini (http://www.linkedin.com/in/svenka3) with the poster:

 

And we had an interesting visitor all the way from home (Bangalore) – Mr. Amit Sharma :-)

 

 

Here is a more detailed list of CVC’s products & Services around UVM:

 

 

 

Overall it was a great successful poster session and the user interest around it is a standing testimonial to the overwhelming customer expectation on UVM.

Why UVM is important for the Semiconductor community?

At DVCon Accellera released its latest standard for VIP interoperability named UVM – Universal Verification Methodology.

12+ vendors demonstrated their commercial solutions around UVM – hasn’t happened for a long time in the industry around single standard – except perhaps for SystemVerilog itself (back in 2003?)

While the technical details can be talked for very long time, here is a practical, real-life experience of “waiting for too long to have this standard”. This could be your simple means of convincing your technical management why they should be looking at UVM seriously in next project.

On the DVCon evening (Mar 1st) I was having dinner with a good old friend of mine, Mahesh. Here are his experiences/pains of working with various verification projects for the past 6+ years:

Mahesh –

it was a nightmare 5-6 years ago for Verification engineers – you move from one project to another within the SAME company (for instance acquired companies in a large company), your way of work – a la - “methodology” changes, hell! How I write my BFM, how it interacts with rest of the environment, how do I control my number-of-transactions etc. etc.

And when you switch jobs – almost guaranteed to go through the unlearn-learn cycle. While this cycle is good in many-a-context, but not to do the same thing – in this case “verification” – just with different base classes/languages.

 

He was listing: e, OpenVera, SystemVerilog languages and eRM, RVM, VMM, AVM and the likes..include OVM if you move the timeline little closer to 2011 :-)

So having a standard methodology is certainly promising for end users and for management to manage resources across projects. Sure there are more compelling technical reasons too – hopefully all for better, but the good things is, even if there are some shortcomings, it is a platform to add things to and bring it to Accellera to grow it beyond UVM 1.0.

Here is a snapshot of what CVC (www.cvcblr.com) has to offer for you around UVM – UnleashingUVM

 

 

Explore technologies for “Verification Closure” at DVCon BoF meeting, Tuesday Mar 1st 6.30 PM (PST)

Big picture – Verification Closure

Panel members: Cadence, NextOp, Breker & CVC

If you are attending DVCon starting tomorrow, here is a panel that you may not want to skip – yes UVM is hot and ready-to-go. How do we leverage that and get to faster Verification Closure – that’s precisely what we will be discussing in this “Birds-of-a-Feather” panel at DVCon www.dvcon.org on Tuesday Mar 1st, 6.30 PM US/Pacific time at Donner Ballroom, DoubleTree Hotel, San Jose.

Here is a summary of what to expect in this panel discussion:

UVM is great! Enables interoperable VIPs to be created, reused. In a typical SoC – several such UVM VIPs get integrated and 1 (or more) embedded processors (ARM-like) configure/control the flow. Individual sequences/virtual sequences at UVM level will do great for peripheral-alone testing.

Taking right from UVM SoC reference flow @ www.uvmworld.org, here is a sample SOC:

How about true “flow/scenario” testing? UVM’s virtual sequencer is “A possibility”. A pragmatic approach as outlined by an excellent article by my good friends @ Applied Micro, Pune (India) is here:

http://www.design-reuse.com/articles/22264/system-verilog-ovm-verification-reusability.html

 

 

The above approach requires lot of coding, synchronization and pretty much directed across transactions/interfaces. How do we randomize “across interfaces/peripherals” to mimic system-level flows/scenarios?

Even if we code up all Sequence libraries, virtual sequences and virtual sequencers – we got only the stimulus, what about complete “Verification Closure”?

On top, overlay Low Power features, requirements and annotate Power State table information – the number of different paths/arcs to be coded and tested is mind boggling – imagine coding them via virtual sequences/sequencer – do-able, but lot of work indeed!

Every DV team does this today in one-way or the-other. But what new technologies are available or becoming available to assist?

Come and listen to experts in this domain at “Birds-of-a-Feather” panel at DVCon www.dvcon.org on Tuesday Mar 1st, 6.30 PM US/Pacific time at Donner Ballroom, DoubleTree Hotel, San Jose.

Here are some key items that would be discussed: If you have more ideas/questions send them across to sevnka3@gmail.com or post as additional comments here at www.cvcblr.com/blog I will incorporate them as much as I can!

• Need truly inter-operable VIPs to start with – This is where UVM comes-in. We at CVC are at DVCOn UVM poster session.
• Need key “metrics” to define, drive and track the progress (Various sources including formal)
• How to focus on “critical, high quality” coverage targets?
• A coherent, high-level mechanism to capture the scenario models that aid in:
• generate stimulus
• capture scenario specific checks/criteria for success and
• Cover them across interfaces, temporal transaction coverage

Come and share your views, learn what your fellow DV folks do all at DVCon!

Feedback from customer on our SystemVerilog training

 

Recently TeamCVC (http://in.linkedin.com/in/cvcblr) conducted a 4-day SystemVerilog workshop at Kochi, South India. Some musings at:

http://www.cvcblr.com/blog/?p=259 

And today we received a cool note from customer voluntarily:

Vinayaraj T R, Project Engineer @Cochin:

I have attended your training on System Verilog for Verification conducted last week at Kochi.  The session was very much helpful for me and even being a fresher I was able to understand the concepts and gain a lot of knowledge from it. I am very sure that it will help me a lot through out my career.

It would be helpful if you could share the lab tutorials of that training.

Thank you once again.

Regards,

Vinayaraj T R,

Vinayaraj is certainly not alone. It is this customer satisfaction that gives us the “passion” to do more!

Until another customer success story, it is sign-off from Bangalore, TeamCVC

Find deeply buried functional bugs with Graph based solver

 

Are you an expert Verification engineer using upto date languages & methodologies available such as Specman/E, SystemVerilog, VMM, OVM, UVM etc.? Are you looking for even more technologies to find “deeply buried functional bugs” in a language agnostic manner, yet be able to reuse the underlying TB code? Read what Dave Whipp, a veteran HW Verification engineer found working over the last few years:

http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=4172 

Specifically:

There is a pressing need for testing tools that are language-agnostic – and such tools are indeed emerging. The shadow of the SystemVerilog steamroller is lifting.
One such tool, that I have been using successfully over the past few years, is Breker’s Trek. Trek randomly generates directed tests using a constrained random walk of a graph (constructed by verification engineers) that describes how an environment interacts with the DUT. This is a step back from the purist approach of SAT-based constraint solvers, but it does provide an effective platform for exploring deep sequences of interactions. It would be good to see panel discussions of SAT-solving Vs graph walking as methodologies for finding deep bugs.

See a snapshot of how a graph based solver can explore constraints that maybe “temporal” and across several transaction hierarchies:

 

 

There is lot more to Trek than this, but this ability itself is beyond today’s existing SAT based solvers. Now combine that with the STRONG and UNIQUE block-to-SoC auto test generation – a new paradigm in verification is rolling out..

See www.brekersystems.com for more. And CVC (www.cvcblr.com) is your partner in India to bring this advanced technology close to you, call us if you want to learn more.

Happy testing!

SystemVerilog Assertions’ field-day at Port city of Cochin!

 

TeamCVC (http://in.linkedin.com/in/cvcblr) is at Cochin, a famous port-city in South India (http://en.wikipedia.org/wiki/Kochi) this week on a “Mission SystemVerilog” at a customer site. It is a 4-day program covering:

• SystemVerilog basics for RTL designers (http://www.cvcblr.com/trng_profiles/CVC_LG_SVD_profile.pdf) 
• System Verilog Assertions (http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf)
• SystemVerilog for Verification engineers (VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf)

The audience is a mix of young, enthusiastic engineers in their early-to-mid career – all very keen to hone their skills on SystemVerilog. Our CTO, Srini (http://in.linkedin.com/in/svenka3) chose to customize the training in a timely manner to get the audience involved and interactive. During Day-2, it was a true “field-day of SystemVerilog Assertions”. Especially when it came to Sequence repetition operators, it was fun all across the room. Needless to say CVC’s SystemVerilog Assertions labs are very well laid out with concrete examples to demonstrate the various sequence operators. However with assertions the fun really lies when you “slightly” change the sequence and/or the trace. Here are some screenshots from this “field-day”.

One of the sequences that we experimented is to demonstrate the difference bet’n non-consecutive [= N] & GOTO [-> N] operator.

One of their smart engineers asked/wanted to change the ##1 to ##0. This is to explain the “endpoint” of a sequence/property as in:

  a |=> b [-> 2] ##1 c;

 

Lucky that we had access to Riviera-Pro running on our laptop, on-the-fly we could tweak the code/trace and demo it live:

 

The fun gets only more when there are multiple threads & multiple attempts. Here is how Riviera-Pro nicely shows it up on Waveform – like a real “THREAD”.

TechnoFun with System Verilog – I turned rand_mode OFF, yet get constraint violation? Crazy Friday evening phenomenon, maybe?

Ravi Teja , ASIC Design-Verification Engineer @ www.cvcblr.com &

  TeamCVC (Nikhil, Satish, Srini et al.)

SystemVerilog is a massive language with several surprises under its belt. Every time you encounter some unexpected result, the first reaction is “Oh! I know System Verilog, this is incorrect behavior of the tool”. Voila! EDA developers get paid *really well* and read the LRM thoroughly before committing their code in. This is not to say that there are no bugs in EDA tools (“bug free EDA tool” is more or less an OXYMORON). But with System Verilog tools becoming more and more stable and advanced, it is very likely the case that you fall under the famous John Cooley’s signature (www.deepchip.com):

 

So was our recent experience with Aldec’s Riviera-Pro simulator with SystemVerilog constraints. 

Let the code speak for itself:

class xactn;
   rand int var1;
   rand int var2;
   constraint c_var1 { var1 inside {[1:10]};}
   constraint c_var2 { var2 inside {[1:10]};}
endclass:xactn

Now var1 & var2 are non-state variables. Whenever I randomize an object of this class, the solver should obey the constraints – no ground breaking stuff, is it? Consider turning the non-state variables to “inactive” state. SystemVerilog supports rand_mode(0/1) for this, a quick explanation for the same is below:

 

Now the real fun starts when you delve into corner cases (a la “the devil lies in the detail”). Even though the rand variable is turned inactive, its value MUST be within the values as demanded by the constraints – in other words the “constraints” are still ACTIVE. This has obvious but overlooked results when used with a rand_mode(ON/OFF). The results after randomization are tabulated below:

So why is the 2nd & 3rd case don’t result in random values for var2, var1 respectively? Isn’t that a bug in the EDA tool? Shouldn’t we be calling their support@aldec.com staff? Hold on.. Let’s believe the tool, after all – some of the best minds in comp-science write these geeky solvers, they must have had something in their mind while writing this piece of code inside :-)

A little bit of RTFM (Read The Fine Manual) reveals the “hidden” secrets of “Art of Debug” with Riviera-Pro. It supports a rc_verbose flag which, when set to a magic value of “2” throws out messages to the log file.

set rc_verbose 2

# RCKERNEL: Error: ../src/test.sv(1): The condition 'c_var1()&&c_var2()&&rc_ext_constraint' is overconstrained.

# KERNEL: 1 (0,0) Var1 =           0 , Var2 =           0

# RCKERNEL: Error: ../src/test.sv(1): The condition 'c_var1()&&c_var2()&&rc_ext_constraint' is overconstrained.

# KERNEL: 2 (0,1) Var1 =           0 , Var2 =           0

# RCKERNEL: Error: ../src/test.sv(1): The condition 'c_var1()&&c_var2()&&rc_ext_constraint' is overconstrained.

# KERNEL: 3 (1,0) Var1 =           0 , Var2 =           0

# KERNEL: 4 (1,1) Var1 =           3 , Var2 =           9

# KERNEL: 5 (0,0) Var1 =           3 , Var2 =           9

# KERNEL: 6 (0,1) Var1 =           3 , Var2 =           4

So the first 3 randomize() calls were failing – important that you handle the return value from object.randomize() (Guideline-1).

First three cases gave a constraint violation. We observed that for cases 1,2,3 atleast one of the constraints is not fulfilled.Hence the randomize method returns zero. What? I turned the rand_mode to OFF, yet it tries randomizing and failing? Crazy Friday Phenomenon Huh?

 

Oh Dear, wait..let’s peel the onion and see why..

This is because each call to randomize involves two steps:
1)solve
    In this step all the constraints are solved (as they are still active). The solver must keep the values of var1 and var2 
between 1 to 10. Their default values are however 0. (i.e var1=0 & var2=0) . This violates the constraints, hence the solver failed.
2)assign
If the solver passed (i.e no constraint violation) and rand_mode is ON then the randomized value is assigned to the variables

Now in case 2 & 3 wherein only one of the variables is set to rand_mode(OFF), the AND operation means that – since the solver ahs failed, no assignment of potential random value to the other variable is performed, hence retaining the value 0f “0”.

Now, the constraint debugger with Riviera-Pro is good to start with, wish it had pin-pointed it to the exact constraint that caused the violation, instead of combining both into single equation as:

# RCKERNEL: Error: ../src/test.sv(1): The condition 'c_var1()&&c_var2()&&rc_ext_constraint' is overconstrained.

Oh, let’s leave some room for improvement :-)

Now, as a closing remark and 2nd coding guideline – if you are changing the rand_mode, see if you can isolate related constraint on that variable and make constraint_mode(OFF) as well. Once again as John Colley puts it: