Adv VHDL Testbench training - Aldec-South Asia begins with a BANG!

For those who missed it, see:

http://www.aldec.in/Company/News.aspx?newsid=34678573-19e6-45a3-99d5-9d5b6accda6c 

This is a significant move I would say as it reinforces few facts:

• Industry is slowly recovering (Hurray!!)
• India/SouthAsia is gaining more and more importance as a wide customer base – apart from major EDA vendors, others are setting up their own centres, driving investments etc.
• India as such provides a vibrant FPGA market and there is enough to tap onto it for EDA vendors!

Recently Aldec-SA conducted a 2-day seminar on “Creating efficient Testbenches using VHDL”. CVC did the delivery of this seminar, being VHDL & Verification experts.

 

We got very good feedback from this event, here is a sample:

**** Straight from customer ************

  Hello Sir,

I am Ramesh R Nair, working in Continental Automotive as an ASIC verification engineer as part of my internship programme of M.Tech(VLSI).

I have attended your  training class on test bench writing last week(ALDEC).

Although we are writing a lot of test benches some utilities were unnoticed.. you bring those things to light.

So it  was very helpful and i shared it with my team members.

Thank you and Congratulations.

Best Regards

Ramesh R Nair

Continental Automotive Components

Bangalore

*****************************

It is always great to hear feedback from customers and it gets better if it is a positive one :-)