VMMing of a VHDL-C based Environment, anyone?

Recently @VGuild Mike asked”

 

Does anyone use ModelSim's FLI for verification? What are the pros and cons of this?
I've been considering adopting SystemVerilog for writing test environments (we code our designs in VHDL and use PSL for assertions and functional coverage) but, from what I can gather, instead of SV I might as well just use ModelSim's FLI and write sophisticated testbenches in C. As an engineer, I am already very familiar with C, and so learning another language for verification (SV) is not desirable.
I suppose SV is more portable to other tools, rather than relying on ModelSim's FLI. And I suppose SV is supported by frameworks such as OVM. Other than that, why not use C/C++ as your verification language with the FLI?

Though the entire EDA marketing machinery is strongly biased on SystemVerilog, let’s realize that there is a sizeable population using VHDL, C etc. Few pointers for those unconvinced:

• Our recent VHLD Advanced TB attendance here in Bangalore (http://www.cvcblr.com/blog/?p=86).
• Continued interest from our customers on FPGA Verification courses: http://www.cvcblr.com/blog/?p=60 
• VHDL random generation, recent webinar @ aldec.com

So what’s the solution for VHDL users, looking at high-end Verification stuff? Is SystemVerilog THE only way? We at CVC believe SystemVerilog is “A way”, not necessarily THE ONLY way. For instance PSL becoming part of VHDL makes it a string candidate than SVA for VHDL users (yes even with recent SVA-09 features included http://www.systemverilog.us/sva_info.html, PSL’s LTL is long proven, well supported than SVA-09). I hear recently more momentum towards PSL from local VHDL users.

So coming back to Mike’s topic – few suggestions:

• No single-size fit all solution
• FLI is a choice if for foreseeable future Modelsim is bought over by your employer. But if there is any question of portability (given that there are strong contenders, pricing factor – did we not hear of BIG EDA vendor slashing prices like crazy – much like Magma style, but for verification?
• I highly recommend to look at VHPI than FLI as it is IEEE standard and well supported by tools like VCSMX, IUS, Aldec (Riviera for sure, Active-HDL too I guess, anyone to confirm??)
• For SystemVerilog like features – explore www.trusster.com for TEAL/TRUSS – akin to VMM/OVM without all bells and whistles, but provides a baseline and is FREE!! Can even run with Icarus for Verilog, hurray!!

So choose the right tool for the right job..