http://edageek.com/2009/11/16/vhdl-verilog-xilinx-secureip/
Not a bad news after all – given that the industry is showing signs of recovery, such offerings are GREAT indeed – during the downturn several mergers, IP accumulation, consolidation have happened. That might have led to mix of languages in new SoCs. Usually the cost of ownership of a full fledged Mixed-HDL simulator (from any of 3 big EDA vendor) costs a lot (some say a “fortune” though I disagree). But this Riviera offering is certainly encouraging indeed.
But is this a “sign-off” tool? Anyone?
2 comments:
Srini, I think it is also important to know the level of support for SystemVerilog. Is this simulator able to compile VMM 1.2beta for instance? Any idea?
Puneet - I agree with the "level of support" part. As we are evaluating Riviera quite seriously for our customers I can't list out the exact features here. But our team has successfully migrated several small/medium Verification environments (some VMM, some OVM too) to run on Riviera. There are challenges and hopefully it will be better with next major release.
Post a Comment