Sub $5000 high-end Mixed HDL simulator - VHDL+Verilog+SV-Design

 

http://edageek.com/2009/11/16/vhdl-verilog-xilinx-secureip/

Not a bad news after all – given that the industry is showing signs of recovery, such offerings are GREAT indeed – during the downturn several mergers, IP accumulation, consolidation have happened. That might have led to mix of languages in new SoCs. Usually the cost of ownership of a full fledged Mixed-HDL simulator (from any of 3 big EDA vendor) costs a lot (some say a “fortune” though I disagree). But this Riviera offering is certainly encouraging indeed.

But is this a “sign-off” tool? Anyone?

And BTW – in DAC they announced $1995 package for Active-HDL with similar support, so it is real!

http://www.aldec.com/Company/News.aspx?newsid=c86c2ee8-5490-4eae-b61e-a7c0aaf7396c