Formal Verification – Model Checking case study from SUN & Jasper – excellent read, to refer..

 

In case you missed it: http://chipdesignmag.com/display.php?articleId=3723

I mentioned this during our recent Advanced VHDL TB class (http://www.cvcblr.com/blog/?p=86) during PSL session and attendees were very interested. Today I got a mail back from Chandramohan asking for the link, sent to him and read it once again (must admit, not in full indepth PCI-e level). Overall an excellent paper, perhaps a strong candidate for a DVCon Best paper award – real design bugs/scenarios listed..truly worth reading.

Such a nice paper didn’t have to have the following on simulation

Simulation, the alternative, brute force approach, ends up wasting resources and introduces additional risk. Even for cases where you think you understand the full state-space, it requires huge effort to develop a test strategy, e.g. complex test scenario with nested loops etc. Manual effort and test are required. Simulation cycles are long and regression test after modifications is slow. Furthermore, the designer generally has to edit down the simulation and remove certain combinations, without absolute knowledge of whether these are important or not. It is hit-or-miss because no design or verification engineer can enumerate all of these combinations.

With due respect to the authors – they seem to be cornering SIM way too side..One can forget the use of intelligent stimulus generation, adopting functional coverage, sequences, virtual sequences and even better the all new Trek (www.brekersystems.com) – their examples do contain similar PCIe stuff and it is quite powerful too. So let’s not write-off simulation, agreed – if and when formal works it is a great technology, but not at the cost of simulation..